Lines Matching +full:0 +full:x11f40000
293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
346 reg = <0x001>;
362 reg = <0x002>;
378 reg = <0x003>;
394 reg = <0x100>;
410 reg = <0x101>;
426 reg = <0x102>;
442 reg = <0x103>;
461 arm,psci-suspend-param = <0x00010001>;
467 CLUSTER_SLEEP0: cluster-sleep-0 {
470 arm,psci-suspend-param = <0x01010001>;
478 arm,psci-suspend-param = <0x01010001>;
486 gpu_opp_table: opp-table-0 {
590 #clock-cells = <0>;
598 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
599 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
600 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
601 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
613 reg = <0 0x08000000 0 0x0010>;
624 reg = <0 0x0c000000 0 0x40000>, /* GICD */
625 <0 0x0c100000 0 0x200000>, /* GICR */
626 <0 0x0c400000 0 0x2000>, /* GICC */
627 <0 0x0c410000 0 0x1000>, /* GICH */
628 <0 0x0c420000 0 0x2000>; /* GICV */
630 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
632 ppi_cluster0: interrupt-partition-0 {
643 reg = <0 0x0c530000 0 0x1000>;
653 reg = <0 0x0c530a80 0 0x50>;
658 reg = <0x0 0xd410000 0x0 0x1000>;
666 reg = <0x0 0xd510000 0x0 0x1000>;
674 reg = <0x0 0xd610000 0x0 0x1000>;
682 reg = <0x0 0xd710000 0x0 0x1000>;
690 reg = <0x0 0xd810000 0x0 0x1000>;
698 reg = <0x0 0xd910000 0x0 0x1000>;
706 reg = <0x0 0xda10000 0x0 0x1000>;
714 reg = <0x0 0xdb10000 0x0 0x1000>;
722 reg = <0 0x10000000 0 0x1000>;
728 reg = <0 0x10001000 0 0x1000>;
735 reg = <0 0x10003000 0 0x1000>;
741 reg = <0 0x10005000 0 0x1000>,
742 <0 0x11f20000 0 0x1000>,
743 <0 0x11e80000 0 0x1000>,
744 <0 0x11e70000 0 0x1000>,
745 <0 0x11e90000 0 0x1000>,
746 <0 0x11d30000 0 0x1000>,
747 <0 0x11d20000 0 0x1000>,
748 <0 0x11c50000 0 0x1000>,
749 <0 0x11f30000 0 0x1000>,
750 <0 0x1000b000 0 0x1000>;
757 gpio-ranges = <&pio 0 0 192>;
765 reg = <0 0x10006000 0 0x1000>;
771 #size-cells = <0>;
781 #power-domain-cells = <0>;
787 #power-domain-cells = <0>;
795 #size-cells = <0>;
801 #size-cells = <0>;
806 #power-domain-cells = <0>;
811 #power-domain-cells = <0>;
817 #power-domain-cells = <0>;
835 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
841 #size-cells = <0>;
854 clock-names = "cam", "cam-0", "cam-1",
859 #power-domain-cells = <0>;
867 clock-names = "isp", "isp-0", "isp-1";
870 #power-domain-cells = <0>;
876 #power-domain-cells = <0>;
882 #power-domain-cells = <0>;
895 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
900 #size-cells = <0>;
908 #power-domain-cells = <0>;
916 #power-domain-cells = <0>;
925 reg = <0 0x10007000 0 0x100>;
931 reg = <0 0x1000c000 0 0x1000>;
937 reg = <0 0x1000d000 0 0x1000>;
947 reg = <0 0x10010000 0 0x1000>;
956 reg = <0 0x10500000 0 0x80000>,
957 <0 0x105c0000 0 0x19080>;
969 reg = <0 0x10017000 0 0x1000>;
977 reg = <0 0x10205000 0 0x1000>;
986 reg = <0 0x10238000 0 0x4000>;
996 reg = <0 0x11001000 0 0x1000>;
1006 reg = <0 0x11002000 0 0x1000>;
1016 reg = <0 0x11003000 0 0x1000>;
1026 reg = <0 0x11004000 0 0x1000>;
1035 reg = <0 0x11005000 0 0x1000>,
1036 <0 0x11000600 0 0x80>;
1043 #size-cells = <0>;
1049 reg = <0 0x11007000 0 0x1000>,
1050 <0 0x11000080 0 0x80>;
1057 #size-cells = <0>;
1063 reg = <0 0x11008000 0 0x1000>,
1064 <0 0x11000100 0 0x80>;
1072 #size-cells = <0>;
1078 reg = <0 0x11009000 0 0x1000>,
1079 <0 0x11000280 0 0x80>;
1087 #size-cells = <0>;
1094 #size-cells = <0>;
1095 reg = <0 0x1100a000 0 0x1000>;
1106 reg = <0 0x1100b000 0 0x1000>;
1119 reg = <0 0x1100b000 0 0x1000>;
1124 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
1135 thermal-sensors = <&thermal 0>;
1198 polling-delay-passive = <0>;
1199 polling-delay = <0>;
1207 polling-delay-passive = <0>;
1208 polling-delay = <0>;
1216 polling-delay-passive = <0>;
1217 polling-delay = <0>;
1225 polling-delay-passive = <0>;
1226 polling-delay = <0>;
1234 polling-delay-passive = <0>;
1235 polling-delay = <0>;
1243 polling-delay-passive = <0>;
1244 polling-delay = <0>;
1254 reg = <0 0x1100e000 0 0x1000>;
1265 reg = <0 0x11006000 0 0x1000>;
1279 reg = <0 0x1100f000 0 0x1000>,
1280 <0 0x11000400 0 0x80>;
1287 #size-cells = <0>;
1294 #size-cells = <0>;
1295 reg = <0 0x11010000 0 0x1000>;
1306 reg = <0 0x11011000 0 0x1000>,
1307 <0 0x11000480 0 0x80>;
1314 #size-cells = <0>;
1321 #size-cells = <0>;
1322 reg = <0 0x11012000 0 0x1000>;
1334 #size-cells = <0>;
1335 reg = <0 0x11013000 0 0x1000>;
1346 reg = <0 0x11014000 0 0x1000>,
1347 <0 0x11000180 0 0x80>;
1355 #size-cells = <0>;
1361 reg = <0 0x11015000 0 0x1000>,
1362 <0 0x11000300 0 0x80>;
1370 #size-cells = <0>;
1376 reg = <0 0x11016000 0 0x1000>,
1377 <0 0x11000500 0 0x80>;
1385 #size-cells = <0>;
1391 reg = <0 0x11017000 0 0x1000>,
1392 <0 0x11000580 0 0x80>;
1400 #size-cells = <0>;
1407 #size-cells = <0>;
1408 reg = <0 0x11018000 0 0x1000>;
1420 #size-cells = <0>;
1421 reg = <0 0x11019000 0 0x1000>;
1432 reg = <0 0x1101a000 0 0x1000>,
1433 <0 0x11000680 0 0x80>;
1440 #size-cells = <0>;
1446 reg = <0 0x1101b000 0 0x1000>,
1447 <0 0x11000700 0 0x80>;
1454 #size-cells = <0>;
1460 reg = <0 0x11201000 0 0x2e00>,
1461 <0 0x11203e00 0 0x0100>;
1469 mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1478 reg = <0 0x11200000 0 0x1000>;
1490 reg = <0 0x11220000 0 0x1000>;
1588 reg = <0 0x11230000 0 0x1000>,
1589 <0 0x11f50000 0 0x1000>;
1600 reg = <0 0x11240000 0 0x1000>,
1601 <0 0x11e10000 0 0x1000>;
1612 reg = <0 0x11e50000 0 0x1000>;
1614 #clock-cells = <0>;
1615 #phy-cells = <0>;
1624 reg = <0 0x11f10000 0 0x1000>;
1628 reg = <0x180 0xc>;
1632 reg = <0x190 0xc>;
1636 reg = <0x580 0x64>;
1645 ranges = <0 0 0x11f40000 0x1000>;
1648 u2port0: usb-phy@0 {
1649 reg = <0x0 0x700>;
1658 reg = <0x0700 0x900>;
1668 reg = <0 0x13000000 0 0x1000>;
1674 reg = <0 0x13040000 0 0x4000>;
1694 reg = <0 0x14000000 0 0x1000>;
1697 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1699 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1704 reg = <0 0x14001000 0 0x1000>;
1705 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1712 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
1713 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
1718 reg = <0 0x14003000 0 0x1000>;
1719 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1727 reg = <0 0x14004000 0 0x1000>;
1728 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1736 reg = <0 0x14005000 0 0x1000>;
1737 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1747 reg = <0 0x14006000 0 0x1000>;
1748 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1758 reg = <0 0x14008000 0 0x1000>;
1763 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1768 reg = <0 0x14009000 0 0x1000>;
1773 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1778 reg = <0 0x1400a000 0 0x1000>;
1783 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1788 reg = <0 0x1400b000 0 0x1000>;
1794 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1799 reg = <0 0x1400c000 0 0x1000>;
1805 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1811 reg = <0 0x1400e000 0 0x1000>;
1815 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1820 reg = <0 0x1400f000 0 0x1000>;
1824 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1829 reg = <0 0x14010000 0 0x1000>;
1833 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1838 reg = <0 0x14011000 0 0x1000>;
1842 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1847 reg = <0 0x14012000 0 0x1000>;
1851 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1856 reg = <0 0x14014000 0 0x1000>;
1870 reg = <0 0x14016000 0 0x1000>;
1875 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1880 reg = <0 0x14017000 0 0x1000>;
1890 reg = <0 0x14019000 0 0x1000>;
1901 reg = <0 0x1401c000 0 0x1000>;
1902 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
1910 reg = <0 0x15020000 0 0x1000>;
1916 reg = <0 0x15021000 0 0x1000>;
1926 reg = <0 0x1502f000 0 0x1000>;
1936 reg = <0 0x16000000 0 0x1000>;
1942 reg = <0 0x16010000 0 0x1000>;
1951 reg = <0 0x17000000 0 0x1000>;
1957 reg = <0 0x17010000 0 0x1000>;
1967 reg = <0 0x17030000 0 0x1000>;
1978 reg = <0 0x19000000 0 0x1000>;
1984 reg = <0 0x19010000 0 0x1000>;
1990 reg = <0 0x19180000 0 0x1000>;
1996 reg = <0 0x19280000 0 0x1000>;
2002 reg = <0 0x1a000000 0 0x1000>;
2008 reg = <0 0x1a001000 0 0x1000>;
2018 reg = <0 0x1a002000 0 0x1000>;