Lines Matching refs:mmsys
988 mmsys: syscon@14000000 { label
989 compatible = "mediatek,mt8173-mmsys", "syscon";
1005 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1006 <&mmsys CLK_MM_MUTEX_32K>;
1015 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1016 <&mmsys CLK_MM_MUTEX_32K>;
1024 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1031 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1038 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1045 clocks = <&mmsys CLK_MM_MDP_WDMA>;
1053 clocks = <&mmsys CLK_MM_MDP_WROT0>;
1061 clocks = <&mmsys CLK_MM_MDP_WROT1>;
1071 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1081 clocks = <&mmsys CLK_MM_DISP_OVL1>;
1091 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1101 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1111 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1121 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1131 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1141 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1150 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1159 clocks = <&mmsys CLK_MM_DISP_AAL>;
1168 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1176 clocks = <&mmsys CLK_MM_DISP_MERGE>;
1183 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1190 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1198 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1207 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1208 <&mmsys CLK_MM_DSI0_DIGITAL>,
1211 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
1222 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1223 <&mmsys CLK_MM_DSI1_DIGITAL>,
1236 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1237 <&mmsys CLK_MM_DPI_ENGINE>,
1254 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1255 <&mmsys CLK_MM_DISP_PWM0MM>;
1265 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1266 <&mmsys CLK_MM_DISP_PWM1MM>;
1276 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1287 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1288 <&mmsys CLK_MM_SMI_LARB0>;
1296 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1297 <&mmsys CLK_MM_SMI_COMMON>;
1304 clocks = <&mmsys CLK_MM_DISP_OD>;
1312 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1313 <&mmsys CLK_MM_HDMI_PLLCK>,
1314 <&mmsys CLK_MM_HDMI_AUDIO>,
1315 <&mmsys CLK_MM_HDMI_SPDIF>;
1321 mediatek,syscon-hdmi = <&mmsys 0x900>;
1345 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1346 <&mmsys CLK_MM_SMI_LARB4>;