Lines Matching +full:opp +full:- +full:1300000000
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
16 #include "mt8173-pinfunc.h"
20 interrupt-parent = <&sysirq>;
21 #address-cells = <2>;
22 #size-cells = <2>;
39 mdp-rdma0 = &mdp_rdma0;
40 mdp-rdma1 = &mdp_rdma1;
41 mdp-rsz0 = &mdp_rsz0;
42 mdp-rsz1 = &mdp_rsz1;
43 mdp-rsz2 = &mdp_rsz2;
44 mdp-wdma0 = &mdp_wdma0;
45 mdp-wrot0 = &mdp_wrot0;
46 mdp-wrot1 = &mdp_wrot1;
53 cluster0_opp: opp-table-0 {
54 compatible = "operating-points-v2";
55 opp-shared;
56 opp-507000000 {
57 opp-hz = /bits/ 64 <507000000>;
58 opp-microvolt = <859000>;
60 opp-702000000 {
61 opp-hz = /bits/ 64 <702000000>;
62 opp-microvolt = <908000>;
64 opp-1001000000 {
65 opp-hz = /bits/ 64 <1001000000>;
66 opp-microvolt = <983000>;
68 opp-1105000000 {
69 opp-hz = /bits/ 64 <1105000000>;
70 opp-microvolt = <1009000>;
72 opp-1209000000 {
73 opp-hz = /bits/ 64 <1209000000>;
74 opp-microvolt = <1034000>;
76 opp-1300000000 {
77 opp-hz = /bits/ 64 <1300000000>;
78 opp-microvolt = <1057000>;
80 opp-1508000000 {
81 opp-hz = /bits/ 64 <1508000000>;
82 opp-microvolt = <1109000>;
84 opp-1703000000 {
85 opp-hz = /bits/ 64 <1703000000>;
86 opp-microvolt = <1125000>;
90 cluster1_opp: opp-table-1 {
91 compatible = "operating-points-v2";
92 opp-shared;
93 opp-507000000 {
94 opp-hz = /bits/ 64 <507000000>;
95 opp-microvolt = <828000>;
97 opp-702000000 {
98 opp-hz = /bits/ 64 <702000000>;
99 opp-microvolt = <867000>;
101 opp-1001000000 {
102 opp-hz = /bits/ 64 <1001000000>;
103 opp-microvolt = <927000>;
105 opp-1209000000 {
106 opp-hz = /bits/ 64 <1209000000>;
107 opp-microvolt = <968000>;
109 opp-1404000000 {
110 opp-hz = /bits/ 64 <1404000000>;
111 opp-microvolt = <1007000>;
113 opp-1612000000 {
114 opp-hz = /bits/ 64 <1612000000>;
115 opp-microvolt = <1049000>;
117 opp-1807000000 {
118 opp-hz = /bits/ 64 <1807000000>;
119 opp-microvolt = <1089000>;
121 opp-2106000000 {
122 opp-hz = /bits/ 64 <2106000000>;
123 opp-microvolt = <1125000>;
128 #address-cells = <1>;
129 #size-cells = <0>;
131 cpu-map {
153 compatible = "arm,cortex-a53";
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
157 #cooling-cells = <2>;
158 dynamic-power-coefficient = <263>;
161 clock-names = "cpu", "intermediate";
162 operating-points-v2 = <&cluster0_opp>;
163 capacity-dmips-mhz = <740>;
168 compatible = "arm,cortex-a53";
170 enable-method = "psci";
171 cpu-idle-states = <&CPU_SLEEP_0>;
172 #cooling-cells = <2>;
173 dynamic-power-coefficient = <263>;
176 clock-names = "cpu", "intermediate";
177 operating-points-v2 = <&cluster0_opp>;
178 capacity-dmips-mhz = <740>;
183 compatible = "arm,cortex-a72";
185 enable-method = "psci";
186 cpu-idle-states = <&CPU_SLEEP_0>;
187 #cooling-cells = <2>;
188 dynamic-power-coefficient = <530>;
191 clock-names = "cpu", "intermediate";
192 operating-points-v2 = <&cluster1_opp>;
193 capacity-dmips-mhz = <1024>;
198 compatible = "arm,cortex-a72";
200 enable-method = "psci";
201 cpu-idle-states = <&CPU_SLEEP_0>;
202 #cooling-cells = <2>;
203 dynamic-power-coefficient = <530>;
206 clock-names = "cpu", "intermediate";
207 operating-points-v2 = <&cluster1_opp>;
208 capacity-dmips-mhz = <1024>;
211 idle-states {
212 entry-method = "psci";
214 CPU_SLEEP_0: cpu-sleep-0 {
215 compatible = "arm,idle-state";
216 local-timer-stop;
217 entry-latency-us = <639>;
218 exit-latency-us = <680>;
219 min-residency-us = <1088>;
220 arm,psci-suspend-param = <0x0010000>;
226 compatible = "arm,cortex-a53-pmu";
229 interrupt-affinity = <&cpu0>, <&cpu1>;
233 compatible = "arm,cortex-a72-pmu";
236 interrupt-affinity = <&cpu2>, <&cpu3>;
240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <26000000>;
251 clock-output-names = "clk26m";
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <32000>;
258 clock-output-names = "clk32k";
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <0>;
265 clock-output-names = "cpum_ck";
268 thermal-zones {
269 cpu_thermal: cpu-thermal {
270 polling-delay-passive = <1000>; /* milliseconds */
271 polling-delay = <1000>; /* milliseconds */
273 thermal-sensors = <&thermal>;
274 sustainable-power = <1500>; /* milliwatts */
277 threshold: trip-point0 {
283 target: trip-point1 {
296 cooling-maps {
299 cooling-device = <&cpu0 THERMAL_NO_LIMIT
307 cooling-device = <&cpu2 THERMAL_NO_LIMIT
317 reserved-memory {
318 #address-cells = <2>;
319 #size-cells = <2>;
322 compatible = "shared-dma-pool";
325 no-map;
330 compatible = "arm,armv8-timer";
331 interrupt-parent = <&gic>;
340 arm,no-tick-in-suspend;
344 #address-cells = <2>;
345 #size-cells = <2>;
346 compatible = "simple-bus";
349 topckgen: clock-controller@10000000 {
350 compatible = "mediatek,mt8173-topckgen";
352 #clock-cells = <1>;
355 infracfg: power-controller@10001000 {
356 compatible = "mediatek,mt8173-infracfg", "syscon";
358 #clock-cells = <1>;
359 #reset-cells = <1>;
362 pericfg: power-controller@10003000 {
363 compatible = "mediatek,mt8173-pericfg", "syscon";
365 #clock-cells = <1>;
366 #reset-cells = <1>;
370 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
375 compatible = "mediatek,mt8173-pinctrl";
377 mediatek,pctl-regmap = <&syscfg_pctl_a>;
378 pins-are-numbered;
379 gpio-controller;
380 #gpio-cells = <2>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
392 input-enable;
393 bias-pull-down;
401 bias-disable;
409 bias-disable;
417 bias-disable;
425 bias-disable;
433 bias-disable;
441 bias-disable;
447 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
451 spm: power-controller {
452 compatible = "mediatek,mt8173-power-controller";
453 #address-cells = <1>;
454 #size-cells = <0>;
455 #power-domain-cells = <1>;
458 power-domain@MT8173_POWER_DOMAIN_VDEC {
461 clock-names = "mm";
462 #power-domain-cells = <0>;
464 power-domain@MT8173_POWER_DOMAIN_VENC {
468 clock-names = "mm", "venc";
469 #power-domain-cells = <0>;
471 power-domain@MT8173_POWER_DOMAIN_ISP {
474 clock-names = "mm";
475 #power-domain-cells = <0>;
477 power-domain@MT8173_POWER_DOMAIN_MM {
480 clock-names = "mm";
481 #power-domain-cells = <0>;
484 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
488 clock-names = "mm", "venclt";
489 #power-domain-cells = <0>;
491 power-domain@MT8173_POWER_DOMAIN_AUDIO {
493 #power-domain-cells = <0>;
495 power-domain@MT8173_POWER_DOMAIN_USB {
497 #power-domain-cells = <0>;
499 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
502 clock-names = "mfg";
503 #address-cells = <1>;
504 #size-cells = <0>;
505 #power-domain-cells = <1>;
507 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 #power-domain-cells = <1>;
513 power-domain@MT8173_POWER_DOMAIN_MFG {
515 #power-domain-cells = <0>;
524 compatible = "mediatek,mt8173-wdt",
525 "mediatek,mt6589-wdt";
530 compatible = "mediatek,mt8173-timer",
531 "mediatek,mt6577-timer";
539 compatible = "mediatek,mt8173-pwrap";
541 reg-names = "pwrap";
544 reset-names = "pwrap";
546 clock-names = "spi", "wrap";
550 compatible = "mediatek,mt8173-cec";
558 compatible = "mediatek,mt8173-vpu";
561 reg-names = "tcm", "cfg_reg";
564 clock-names = "main";
565 memory-region = <&vpu_dma_reserved>;
568 sysirq: intpol-controller@10200620 {
569 compatible = "mediatek,mt8173-sysirq",
570 "mediatek,mt6577-sysirq";
571 interrupt-controller;
572 #interrupt-cells = <3>;
573 interrupt-parent = <&gic>;
578 compatible = "mediatek,mt8173-m4u";
582 clock-names = "bclk";
586 #iommu-cells = <1>;
590 compatible = "mediatek,mt8173-efuse";
592 #address-cells = <1>;
593 #size-cells = <1>;
599 apmixedsys: clock-controller@10209000 {
600 compatible = "mediatek,mt8173-apmixedsys";
602 #clock-cells = <1>;
605 hdmi_phy: hdmi-phy@10209100 {
606 compatible = "mediatek,mt8173-hdmi-phy";
609 clock-names = "pll_ref";
610 clock-output-names = "hdmitx_dig_cts";
613 #clock-cells = <0>;
614 #phy-cells = <0>;
619 compatible = "mediatek,mt8173-gce";
623 clock-names = "gce";
624 #mbox-cells = <2>;
627 mipi_tx0: dsi-phy@10215000 {
628 compatible = "mediatek,mt8173-mipi-tx";
631 clock-output-names = "mipi_tx0_pll";
632 #clock-cells = <0>;
633 #phy-cells = <0>;
637 mipi_tx1: dsi-phy@10216000 {
638 compatible = "mediatek,mt8173-mipi-tx";
641 clock-output-names = "mipi_tx1_pll";
642 #clock-cells = <0>;
643 #phy-cells = <0>;
647 gic: interrupt-controller@10221000 {
648 compatible = "arm,gic-400";
649 #interrupt-cells = <3>;
650 interrupt-parent = <&gic>;
651 interrupt-controller;
661 compatible = "mediatek,mt8173-auxadc";
664 clock-names = "main";
665 #io-channel-cells = <1>;
669 compatible = "mediatek,mt8173-uart",
670 "mediatek,mt6577-uart";
674 clock-names = "baud", "bus";
679 compatible = "mediatek,mt8173-uart",
680 "mediatek,mt6577-uart";
684 clock-names = "baud", "bus";
689 compatible = "mediatek,mt8173-uart",
690 "mediatek,mt6577-uart";
694 clock-names = "baud", "bus";
699 compatible = "mediatek,mt8173-uart",
700 "mediatek,mt6577-uart";
704 clock-names = "baud", "bus";
709 compatible = "mediatek,mt8173-i2c";
713 clock-div = <16>;
716 clock-names = "main", "dma";
717 pinctrl-names = "default";
718 pinctrl-0 = <&i2c0_pins_a>;
719 #address-cells = <1>;
720 #size-cells = <0>;
725 compatible = "mediatek,mt8173-i2c";
729 clock-div = <16>;
732 clock-names = "main", "dma";
733 pinctrl-names = "default";
734 pinctrl-0 = <&i2c1_pins_a>;
735 #address-cells = <1>;
736 #size-cells = <0>;
741 compatible = "mediatek,mt8173-i2c";
745 clock-div = <16>;
748 clock-names = "main", "dma";
749 pinctrl-names = "default";
750 pinctrl-0 = <&i2c2_pins_a>;
751 #address-cells = <1>;
752 #size-cells = <0>;
757 compatible = "mediatek,mt8173-spi";
758 #address-cells = <1>;
759 #size-cells = <0>;
765 clock-names = "parent-clk", "sel-clk", "spi-clk";
770 #thermal-sensor-cells = <0>;
771 compatible = "mediatek,mt8173-thermal";
775 clock-names = "therm", "auxadc";
779 nvmem-cells = <&thermal_calibration>;
780 nvmem-cell-names = "calibration-data";
784 compatible = "mediatek,mt8173-nor";
786 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
787 assigned-clock-parents = <&clk26m>;
791 clock-names = "spi", "sf", "axi";
792 #address-cells = <1>;
793 #size-cells = <0>;
798 compatible = "mediatek,mt8173-i2c";
802 clock-div = <16>;
805 clock-names = "main", "dma";
806 pinctrl-names = "default";
807 pinctrl-0 = <&i2c3_pins_a>;
808 #address-cells = <1>;
809 #size-cells = <0>;
814 compatible = "mediatek,mt8173-i2c";
818 clock-div = <16>;
821 clock-names = "main", "dma";
822 pinctrl-names = "default";
823 pinctrl-0 = <&i2c4_pins_a>;
824 #address-cells = <1>;
825 #size-cells = <0>;
830 compatible = "mediatek,mt8173-hdmi-ddc";
834 clock-names = "ddc-i2c";
838 compatible = "mediatek,mt8173-i2c";
842 clock-div = <16>;
845 clock-names = "main", "dma";
846 pinctrl-names = "default";
847 pinctrl-0 = <&i2c6_pins_a>;
848 #address-cells = <1>;
849 #size-cells = <0>;
853 afe: audio-controller@11220000 {
854 compatible = "mediatek,mt8173-afe-pcm";
857 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
868 clock-names = "infra_sys_audio_clk",
878 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
880 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
885 compatible = "mediatek,mt8173-mmc";
890 clock-names = "source", "hclk";
895 compatible = "mediatek,mt8173-mmc";
900 clock-names = "source", "hclk";
905 compatible = "mediatek,mt8173-mmc";
910 clock-names = "source", "hclk";
915 compatible = "mediatek,mt8173-mmc";
920 clock-names = "source", "hclk";
925 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
928 reg-names = "mac", "ippc";
933 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
935 clock-names = "sys_ck", "ref_ck";
936 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
937 #address-cells = <2>;
938 #size-cells = <2>;
943 compatible = "mediatek,mt8173-xhci",
944 "mediatek,mtk-xhci";
946 reg-names = "mac";
948 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
950 clock-names = "sys_ck", "ref_ck";
955 u3phy: t-phy@11290000 {
956 compatible = "mediatek,mt8173-u3phy";
958 #address-cells = <2>;
959 #size-cells = <2>;
963 u2port0: usb-phy@11290800 {
966 clock-names = "ref";
967 #phy-cells = <1>;
971 u3port0: usb-phy@11290900 {
974 clock-names = "ref";
975 #phy-cells = <1>;
979 u2port1: usb-phy@11291000 {
982 clock-names = "ref";
983 #phy-cells = <1>;
989 compatible = "mediatek,mt8173-mmsys", "syscon";
991 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
992 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
993 assigned-clock-rates = <400000000>;
994 #clock-cells = <1>;
995 #reset-cells = <1>;
998 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1002 compatible = "mediatek,mt8173-mdp-rdma",
1003 "mediatek,mt8173-mdp";
1007 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1013 compatible = "mediatek,mt8173-mdp-rdma";
1017 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1022 compatible = "mediatek,mt8173-mdp-rsz";
1025 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1029 compatible = "mediatek,mt8173-mdp-rsz";
1032 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1036 compatible = "mediatek,mt8173-mdp-rsz";
1039 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1043 compatible = "mediatek,mt8173-mdp-wdma";
1046 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1051 compatible = "mediatek,mt8173-mdp-wrot";
1054 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1059 compatible = "mediatek,mt8173-mdp-wrot";
1062 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1067 compatible = "mediatek,mt8173-disp-ovl";
1070 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1073 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1077 compatible = "mediatek,mt8173-disp-ovl";
1080 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1083 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1087 compatible = "mediatek,mt8173-disp-rdma";
1090 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1093 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1097 compatible = "mediatek,mt8173-disp-rdma";
1100 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1103 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1107 compatible = "mediatek,mt8173-disp-rdma";
1110 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1113 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1117 compatible = "mediatek,mt8173-disp-wdma";
1120 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1123 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1127 compatible = "mediatek,mt8173-disp-wdma";
1130 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1133 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1137 compatible = "mediatek,mt8173-disp-color";
1140 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1142 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1146 compatible = "mediatek,mt8173-disp-color";
1149 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1151 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1155 compatible = "mediatek,mt8173-disp-aal";
1158 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1160 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1164 compatible = "mediatek,mt8173-disp-gamma";
1167 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1169 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1173 compatible = "mediatek,mt8173-disp-merge";
1175 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1180 compatible = "mediatek,mt8173-disp-split";
1182 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1187 compatible = "mediatek,mt8173-disp-split";
1189 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1194 compatible = "mediatek,mt8173-disp-ufoe";
1197 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1199 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1203 compatible = "mediatek,mt8173-dsi";
1206 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1210 clock-names = "engine", "digital", "hs";
1213 phy-names = "dphy";
1218 compatible = "mediatek,mt8173-dsi";
1221 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1225 clock-names = "engine", "digital", "hs";
1227 phy-names = "dphy";
1232 compatible = "mediatek,mt8173-dpi";
1235 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1239 clock-names = "pixel", "engine", "pll";
1244 remote-endpoint = <&hdmi0_in>;
1250 compatible = "mediatek,mt8173-disp-pwm",
1251 "mediatek,mt6595-disp-pwm";
1253 #pwm-cells = <2>;
1256 clock-names = "main", "mm";
1261 compatible = "mediatek,mt8173-disp-pwm",
1262 "mediatek,mt6595-disp-pwm";
1264 #pwm-cells = <2>;
1267 clock-names = "main", "mm";
1272 compatible = "mediatek,mt8173-disp-mutex";
1275 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1277 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1278 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1283 compatible = "mediatek,mt8173-smi-larb";
1286 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1289 clock-names = "apb", "smi";
1293 compatible = "mediatek,mt8173-smi-common";
1295 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1298 clock-names = "apb", "smi";
1302 compatible = "mediatek,mt8173-disp-od";
1305 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1309 compatible = "mediatek,mt8173-hdmi";
1316 clock-names = "pixel", "pll", "bclk", "spdif";
1317 pinctrl-names = "default";
1318 pinctrl-0 = <&hdmi_pin>;
1320 phy-names = "hdmi";
1321 mediatek,syscon-hdmi = <&mmsys 0x900>;
1322 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1323 assigned-clock-parents = <&hdmi_phy>;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1334 remote-endpoint = <&dpi0_out>;
1341 compatible = "mediatek,mt8173-smi-larb";
1344 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1347 clock-names = "apb", "smi";
1350 imgsys: clock-controller@15000000 {
1351 compatible = "mediatek,mt8173-imgsys", "syscon";
1353 #clock-cells = <1>;
1357 compatible = "mediatek,mt8173-smi-larb";
1360 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1363 clock-names = "apb", "smi";
1366 vdecsys: clock-controller@16000000 {
1367 compatible = "mediatek,mt8173-vdecsys", "syscon";
1369 #clock-cells = <1>;
1373 compatible = "mediatek,mt8173-vcodec-dec";
1396 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1405 clock-names = "vcodecpll",
1413 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1418 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1421 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1425 compatible = "mediatek,mt8173-smi-larb";
1428 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1431 clock-names = "apb", "smi";
1434 vencsys: clock-controller@18000000 {
1435 compatible = "mediatek,mt8173-vencsys", "syscon";
1437 #clock-cells = <1>;
1441 compatible = "mediatek,mt8173-smi-larb";
1444 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1447 clock-names = "apb", "smi";
1451 compatible = "mediatek,mt8173-vcodec-enc";
1467 clock-names = "venc_sel";
1468 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1469 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1470 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1474 compatible = "mediatek,mt8173-jpgdec";
1479 clock-names = "jpgdec-smi",
1481 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1486 vencltsys: clock-controller@19000000 {
1487 compatible = "mediatek,mt8173-vencltsys", "syscon";
1489 #clock-cells = <1>;
1493 compatible = "mediatek,mt8173-smi-larb";
1496 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1499 clock-names = "apb", "smi";
1503 compatible = "mediatek,mt8173-vcodec-enc-vp8";
1517 clock-names = "venc_lt_sel";
1518 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1519 assigned-clock-parents =
1521 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;