Lines Matching +full:0 +full:x1400f000
53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
243 cpu_off = <0x84000002>;
244 cpu_on = <0x84000003>;
249 #clock-cells = <0>;
256 #clock-cells = <0>;
263 #clock-cells = <0>;
264 clock-frequency = <0>;
323 reg = <0 0xb7000000 0 0x500000>;
324 alignment = <0x1000>;
351 reg = <0 0x10000000 0 0x1000>;
357 reg = <0 0x10001000 0 0x1000>;
364 reg = <0 0x10003000 0 0x1000>;
371 reg = <0 0x10005000 0 0x1000>;
376 reg = <0 0x1000b000 0 0x1000>;
448 reg = <0 0x10006000 0 0x1000>;
454 #size-cells = <0>;
462 #power-domain-cells = <0>;
469 #power-domain-cells = <0>;
475 #power-domain-cells = <0>;
481 #power-domain-cells = <0>;
489 #power-domain-cells = <0>;
493 #power-domain-cells = <0>;
497 #power-domain-cells = <0>;
504 #size-cells = <0>;
510 #size-cells = <0>;
515 #power-domain-cells = <0>;
526 reg = <0 0x10007000 0 0x100>;
532 reg = <0 0x10008000 0 0x1000>;
540 reg = <0 0x1000d000 0 0x1000>;
551 reg = <0 0x10013000 0 0xbc>;
559 reg = <0 0x10020000 0 0x30000>,
560 <0 0x10050000 0 0x100>;
574 reg = <0 0x10200620 0 0x20>;
579 reg = <0 0x10205000 0 0x1000>;
591 reg = <0 0x10206000 0 0x1000>;
595 reg = <0x528 0xc>;
601 reg = <0 0x10209000 0 0x1000>;
607 reg = <0 0x10209100 0 0x24>;
611 mediatek,ibias = <0xa>;
612 mediatek,ibias_up = <0x1c>;
613 #clock-cells = <0>;
614 #phy-cells = <0>;
620 reg = <0 0x10212000 0 0x1000>;
629 reg = <0 0x10215000 0 0x1000>;
632 #clock-cells = <0>;
633 #phy-cells = <0>;
639 reg = <0 0x10216000 0 0x1000>;
642 #clock-cells = <0>;
643 #phy-cells = <0>;
652 reg = <0 0x10221000 0 0x1000>,
653 <0 0x10222000 0 0x2000>,
654 <0 0x10224000 0 0x2000>,
655 <0 0x10226000 0 0x2000>;
662 reg = <0 0x11001000 0 0x1000>;
671 reg = <0 0x11002000 0 0x400>;
681 reg = <0 0x11003000 0 0x400>;
691 reg = <0 0x11004000 0 0x400>;
701 reg = <0 0x11005000 0 0x400>;
710 reg = <0 0x11007000 0 0x70>,
711 <0 0x11000100 0 0x80>;
718 pinctrl-0 = <&i2c0_pins_a>;
720 #size-cells = <0>;
726 reg = <0 0x11008000 0 0x70>,
727 <0 0x11000180 0 0x80>;
734 pinctrl-0 = <&i2c1_pins_a>;
736 #size-cells = <0>;
742 reg = <0 0x11009000 0 0x70>,
743 <0 0x11000200 0 0x80>;
750 pinctrl-0 = <&i2c2_pins_a>;
752 #size-cells = <0>;
759 #size-cells = <0>;
760 reg = <0 0x1100a000 0 0x1000>;
770 #thermal-sensor-cells = <0>;
772 reg = <0 0x1100b000 0 0x1000>;
773 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
785 reg = <0 0x1100d000 0 0xe0>;
793 #size-cells = <0>;
799 reg = <0 0x11010000 0 0x70>,
800 <0 0x11000280 0 0x80>;
807 pinctrl-0 = <&i2c3_pins_a>;
809 #size-cells = <0>;
815 reg = <0 0x11011000 0 0x70>,
816 <0 0x11000300 0 0x80>;
823 pinctrl-0 = <&i2c4_pins_a>;
825 #size-cells = <0>;
832 reg = <0 0x11012000 0 0x1C>;
839 reg = <0 0x11013000 0 0x70>,
840 <0 0x11000080 0 0x80>;
847 pinctrl-0 = <&i2c6_pins_a>;
849 #size-cells = <0>;
855 reg = <0 0x11220000 0 0x1000>;
886 reg = <0 0x11230000 0 0x1000>;
896 reg = <0 0x11240000 0 0x1000>;
906 reg = <0 0x11250000 0 0x1000>;
916 reg = <0 0x11260000 0 0x1000>;
926 reg = <0 0x11271000 0 0x3000>,
927 <0 0x11280700 0 0x0100>;
936 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
945 reg = <0 0x11270000 0 0x1000>;
957 reg = <0 0x11290000 0 0x800>;
964 reg = <0 0x11290800 0 0x100>;
972 reg = <0 0x11290900 0 0x700>;
980 reg = <0 0x11291000 0 0x100>;
990 reg = <0 0x14000000 0 0x1000>;
996 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
998 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1004 reg = <0 0x14001000 0 0x1000>;
1014 reg = <0 0x14002000 0 0x1000>;
1023 reg = <0 0x14003000 0 0x1000>;
1030 reg = <0 0x14004000 0 0x1000>;
1037 reg = <0 0x14005000 0 0x1000>;
1044 reg = <0 0x14006000 0 0x1000>;
1052 reg = <0 0x14007000 0 0x1000>;
1060 reg = <0 0x14008000 0 0x1000>;
1068 reg = <0 0x1400c000 0 0x1000>;
1073 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1078 reg = <0 0x1400d000 0 0x1000>;
1083 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1088 reg = <0 0x1400e000 0 0x1000>;
1093 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1098 reg = <0 0x1400f000 0 0x1000>;
1103 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1108 reg = <0 0x14010000 0 0x1000>;
1113 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1118 reg = <0 0x14011000 0 0x1000>;
1123 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1128 reg = <0 0x14012000 0 0x1000>;
1133 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1138 reg = <0 0x14013000 0 0x1000>;
1142 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1147 reg = <0 0x14014000 0 0x1000>;
1151 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1156 reg = <0 0x14015000 0 0x1000>;
1160 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1165 reg = <0 0x14016000 0 0x1000>;
1169 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1174 reg = <0 0x14017000 0 0x1000>;
1181 reg = <0 0x14018000 0 0x1000>;
1188 reg = <0 0x14019000 0 0x1000>;
1195 reg = <0 0x1401a000 0 0x1000>;
1199 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1204 reg = <0 0x1401b000 0 0x1000>;
1219 reg = <0 0x1401c000 0 0x1000>;
1233 reg = <0 0x1401d000 0 0x1000>;
1252 reg = <0 0x1401e000 0 0x1000>;
1263 reg = <0 0x1401f000 0 0x1000>;
1273 reg = <0 0x14020000 0 0x1000>;
1277 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1284 reg = <0 0x14021000 0 0x1000>;
1294 reg = <0 0x14022000 0 0x1000>;
1303 reg = <0 0x14023000 0 0x1000>;
1305 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1310 reg = <0 0x14025000 0 0x400>;
1318 pinctrl-0 = <&hdmi_pin>;
1321 mediatek,syscon-hdmi = <&mmsys 0x900>;
1328 #size-cells = <0>;
1330 port@0 {
1331 reg = <0>;
1342 reg = <0 0x14027000 0 0x1000>;
1352 reg = <0 0x15000000 0 0x1000>;
1358 reg = <0 0x15001000 0 0x1000>;
1368 reg = <0 0x16000000 0 0x1000>;
1374 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1375 <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1376 <0 0x16021000 0 0x800>, /* VDEC_LD */
1377 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1378 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1379 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1380 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1381 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1382 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1383 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1384 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1385 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1421 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1426 reg = <0 0x16010000 0 0x1000>;
1436 reg = <0 0x18000000 0 0x1000>;
1442 reg = <0 0x18001000 0 0x1000>;
1452 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
1475 reg = <0 0x18004000 0 0x1000>;
1488 reg = <0 0x19000000 0 0x1000>;
1494 reg = <0 0x19001000 0 0x1000>;
1504 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */