Lines Matching +full:pins +full:- +full:are +full:- +full:numbered
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
33 compatible = "mediatek,mt8167-apmixedsys", "syscon";
35 #clock-cells = <1>;
39 compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
42 spm: power-controller {
43 compatible = "mediatek,mt8167-power-controller";
44 #address-cells = <1>;
45 #size-cells = <0>;
46 #power-domain-cells = <1>;
49 power-domain@MT8167_POWER_DOMAIN_MM {
52 clock-names = "mm";
53 #power-domain-cells = <0>;
57 power-domain@MT8167_POWER_DOMAIN_VDEC {
61 clock-names = "mm", "vdec";
62 #power-domain-cells = <0>;
65 power-domain@MT8167_POWER_DOMAIN_ISP {
68 clock-names = "mm";
69 #power-domain-cells = <0>;
72 power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
76 clock-names = "axi_mfg", "mfg";
77 #address-cells = <1>;
78 #size-cells = <0>;
79 #power-domain-cells = <1>;
82 power-domain@MT8167_POWER_DOMAIN_MFG_2D {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 #power-domain-cells = <1>;
88 power-domain@MT8167_POWER_DOMAIN_MFG {
90 #power-domain-cells = <0>;
96 power-domain@MT8167_POWER_DOMAIN_CONN {
98 #power-domain-cells = <0>;
105 compatible = "mediatek,mt8167-imgsys", "syscon";
107 #clock-cells = <1>;
111 compatible = "mediatek,mt8167-vdecsys", "syscon";
113 #clock-cells = <1>;
117 compatible = "mediatek,mt8167-pinctrl";
119 mediatek,pctl-regmap = <&syscfg_pctl>;
120 pins-are-numbered;
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
129 compatible = "mediatek,mt8167-mmsys", "syscon";
131 #clock-cells = <1>;
135 compatible = "mediatek,mt8167-smi-common";
139 clock-names = "apb", "smi";
140 power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
144 compatible = "mediatek,mt8167-smi-larb";
149 clock-names = "apb", "smi";
150 power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
154 compatible = "mediatek,mt8167-smi-larb";
159 clock-names = "apb", "smi";
160 power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
164 compatible = "mediatek,mt8167-smi-larb";
169 clock-names = "apb", "smi";
170 power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
174 compatible = "mediatek,mt8167-m4u";
178 #iommu-cells = <1>;