Lines Matching refs:pericfg
232 pericfg: pericfg@10002000 { label
233 compatible = "mediatek,mt7622-pericfg",
386 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
397 <&pericfg CLK_PERI_UART0_PD>;
408 <&pericfg CLK_PERI_UART1_PD>;
419 <&pericfg CLK_PERI_UART2_PD>;
430 <&pericfg CLK_PERI_UART3_PD>;
440 <&pericfg CLK_PERI_PWM_PD>,
441 <&pericfg CLK_PERI_PWM1_PD>,
442 <&pericfg CLK_PERI_PWM2_PD>,
443 <&pericfg CLK_PERI_PWM3_PD>,
444 <&pericfg CLK_PERI_PWM4_PD>,
445 <&pericfg CLK_PERI_PWM5_PD>,
446 <&pericfg CLK_PERI_PWM6_PD>;
458 clocks = <&pericfg CLK_PERI_I2C0_PD>,
459 <&pericfg CLK_PERI_AP_DMA_PD>;
472 clocks = <&pericfg CLK_PERI_I2C1_PD>,
473 <&pericfg CLK_PERI_AP_DMA_PD>;
486 clocks = <&pericfg CLK_PERI_I2C2_PD>,
487 <&pericfg CLK_PERI_AP_DMA_PD>;
500 <&pericfg CLK_PERI_SPI0_PD>;
512 clocks = <&pericfg CLK_PERI_THERM_PD>,
513 <&pericfg CLK_PERI_AUXADC_PD>;
515 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
528 clocks = <&pericfg CLK_PERI_BTIF_PD>;
546 clocks = <&pericfg CLK_PERI_NFI_PD>,
547 <&pericfg CLK_PERI_SNFI_PD>;
559 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
571 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
580 clocks = <&pericfg CLK_PERI_FLASH_PD>,
594 <&pericfg CLK_PERI_SPI1_PD>;
607 <&pericfg CLK_PERI_UART4_PD>;
705 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
708 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
717 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
720 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;