Lines Matching +full:mediatek +full:- +full:thermal
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
25 opp-shared;
26 opp-300000000 {
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
31 opp-437500000 {
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
36 opp-600000000 {
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
41 opp-812500000 {
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
46 opp-1025000000 {
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
51 opp-1137500000 {
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
56 opp-1262500000 {
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
61 opp-1350000000 {
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
68 #address-cells = <2>;
69 #size-cells = <0>;
73 compatible = "arm,cortex-a53";
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>;
80 enable-method = "psci";
81 clock-frequency = <1300000000>;
82 cci-control-port = <&cci_control2>;
83 next-level-cache = <&L2>;
88 compatible = "arm,cortex-a53";
92 clock-names = "cpu", "intermediate";
93 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>;
95 enable-method = "psci";
96 clock-frequency = <1300000000>;
97 cci-control-port = <&cci_control2>;
98 next-level-cache = <&L2>;
101 L2: l2-cache {
103 cache-level = <2>;
108 compatible = "fixed-clock";
109 clock-frequency = <40000000>;
110 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <25000000>;
117 clock-output-names = "clkxtal";
121 compatible = "arm,psci-0.2";
126 compatible = "arm,cortex-a53-pmu";
129 interrupt-affinity = <&cpu0>, <&cpu1>;
132 reserved-memory {
133 #address-cells = <2>;
134 #size-cells = <2>;
140 no-map;
144 thermal-zones {
145 cpu_thermal: cpu-thermal {
146 polling-delay-passive = <1000>;
147 polling-delay = <1000>;
149 thermal-sensors = <&thermal 0>;
152 cpu_passive: cpu-passive {
158 cpu_active: cpu-active {
164 cpu_hot: cpu-hot {
170 cpu-crit {
177 cooling-maps {
180 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
186 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
192 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
200 compatible = "arm,armv8-timer";
201 interrupt-parent = <&gic>;
213 compatible = "mediatek,mt7622-infracfg",
216 #clock-cells = <1>;
217 #reset-cells = <1>;
221 compatible = "mediatek,mt7622-pwrap";
223 reg-names = "pwrap";
225 clock-names = "spi", "wrap";
227 reset-names = "pwrap";
233 compatible = "mediatek,mt7622-pericfg",
236 #clock-cells = <1>;
237 #reset-cells = <1>;
240 scpsys: power-controller@10006000 {
241 compatible = "mediatek,mt7622-scpsys",
243 #power-domain-cells = <1>;
251 clock-names = "hif_sel";
255 compatible = "mediatek,mt7622-cir";
260 clock-names = "clk", "bus";
264 sysirq: interrupt-controller@10200620 {
265 compatible = "mediatek,mt7622-sysirq",
266 "mediatek,mt6577-sysirq";
267 interrupt-controller;
268 #interrupt-cells = <3>;
269 interrupt-parent = <&gic>;
274 compatible = "mediatek,mt7622-efuse",
275 "mediatek,efuse";
277 #address-cells = <1>;
278 #size-cells = <1>;
286 compatible = "mediatek,mt7622-apmixedsys",
289 #clock-cells = <1>;
293 compatible = "mediatek,mt7622-topckgen",
296 #clock-cells = <1>;
300 compatible = "mediatek,mt7622-rng",
301 "mediatek,mt7623-rng";
304 clock-names = "rng";
308 compatible = "mediatek,mt7622-pinctrl";
311 reg-names = "base", "eint";
312 gpio-controller;
313 #gpio-cells = <2>;
314 gpio-ranges = <&pio 0 0 103>;
315 interrupt-controller;
317 interrupt-parent = <&gic>;
318 #interrupt-cells = <2>;
322 compatible = "mediatek,mt7622-wdt",
323 "mediatek,mt6589-wdt";
328 compatible = "mediatek,mt7622-rtc",
329 "mediatek,soc-rtc";
333 clock-names = "rtc";
336 gic: interrupt-controller@10300000 {
337 compatible = "arm,gic-400";
338 interrupt-controller;
339 #interrupt-cells = <3>;
340 interrupt-parent = <&gic>;
348 compatible = "arm,cci-400";
349 #address-cells = <1>;
350 #size-cells = <1>;
354 cci_control0: slave-if@1000 {
355 compatible = "arm,cci-400-ctrl-if";
356 interface-type = "ace-lite";
360 cci_control1: slave-if@4000 {
361 compatible = "arm,cci-400-ctrl-if";
362 interface-type = "ace";
366 cci_control2: slave-if@5000 {
367 compatible = "arm,cci-400-ctrl-if", "syscon";
368 interface-type = "ace";
373 compatible = "arm,cci-400-pmu,r1";
384 compatible = "mediatek,mt7622-auxadc";
387 clock-names = "main";
388 #io-channel-cells = <1>;
392 compatible = "mediatek,mt7622-uart",
393 "mediatek,mt6577-uart";
398 clock-names = "baud", "bus";
403 compatible = "mediatek,mt7622-uart",
404 "mediatek,mt6577-uart";
409 clock-names = "baud", "bus";
414 compatible = "mediatek,mt7622-uart",
415 "mediatek,mt6577-uart";
420 clock-names = "baud", "bus";
425 compatible = "mediatek,mt7622-uart",
426 "mediatek,mt6577-uart";
431 clock-names = "baud", "bus";
436 compatible = "mediatek,mt7622-pwm";
447 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
453 compatible = "mediatek,mt7622-i2c";
457 clock-div = <16>;
460 clock-names = "main", "dma";
461 #address-cells = <1>;
462 #size-cells = <0>;
467 compatible = "mediatek,mt7622-i2c";
471 clock-div = <16>;
474 clock-names = "main", "dma";
475 #address-cells = <1>;
476 #size-cells = <0>;
481 compatible = "mediatek,mt7622-i2c";
485 clock-div = <16>;
488 clock-names = "main", "dma";
489 #address-cells = <1>;
490 #size-cells = <0>;
495 compatible = "mediatek,mt7622-spi";
501 clock-names = "parent-clk", "sel-clk", "spi-clk";
502 #address-cells = <1>;
503 #size-cells = <0>;
507 thermal: thermal@1100b000 { label
508 #thermal-sensor-cells = <1>;
509 compatible = "mediatek,mt7622-thermal";
514 clock-names = "therm", "auxadc";
516 reset-names = "therm";
517 mediatek,auxadc = <&auxadc>;
518 mediatek,apmixedsys = <&apmixedsys>;
519 nvmem-cells = <&thermal_calibration>;
520 nvmem-cell-names = "calibration-data";
524 compatible = "mediatek,mt7622-btif",
525 "mediatek,mtk-btif";
529 clock-names = "main";
530 reg-shift = <2>;
531 reg-io-width = <4>;
535 compatible = "mediatek,mt7622-bluetooth";
536 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
538 clock-names = "ref";
543 compatible = "mediatek,mt7622-nfc";
548 clock-names = "nfi_clk", "pad_clk";
549 ecc-engine = <&bch>;
550 #address-cells = <1>;
551 #size-cells = <0>;
556 compatible = "mediatek,mt7622-snand";
560 clock-names = "nfi_clk", "pad_clk";
561 nand-ecc-engine = <&bch>;
562 #address-cells = <1>;
563 #size-cells = <0>;
568 compatible = "mediatek,mt7622-ecc";
572 clock-names = "nfiecc_clk";
577 compatible = "mediatek,mt7622-nor",
578 "mediatek,mt8173-nor";
582 clock-names = "spi", "sf";
583 #address-cells = <1>;
584 #size-cells = <0>;
589 compatible = "mediatek,mt7622-spi";
595 clock-names = "parent-clk", "sel-clk", "spi-clk";
596 #address-cells = <1>;
597 #size-cells = <0>;
602 compatible = "mediatek,mt7622-uart",
603 "mediatek,mt6577-uart";
608 clock-names = "baud", "bus";
612 audsys: clock-controller@11220000 {
613 compatible = "mediatek,mt7622-audsys", "syscon";
615 #clock-cells = <1>;
617 afe: audio-controller {
618 compatible = "mediatek,mt7622-audio";
621 interrupt-names = "afe", "asys";
657 clock-names = "infra_sys_audio_clk",
691 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
695 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
697 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
702 compatible = "mediatek,mt7622-mmc";
707 clock-names = "source", "hclk";
709 reset-names = "hrst";
714 compatible = "mediatek,mt7622-mmc";
719 clock-names = "source", "hclk";
721 reset-names = "hrst";
726 compatible = "mediatek,mt7622-wmac";
730 mediatek,infracfg = <&infracfg>;
733 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
737 compatible = "mediatek,mt7622-ssusbsys",
740 #clock-cells = <1>;
741 #reset-cells = <1>;
745 compatible = "mediatek,mt7622-xhci",
746 "mediatek,mtk-xhci";
749 reg-names = "mac", "ippc";
751 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
756 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
764 u3phy: t-phy@1a0c4000 {
765 compatible = "mediatek,mt7622-tphy",
766 "mediatek,generic-tphy-v1";
768 #address-cells = <2>;
769 #size-cells = <2>;
773 u2port0: usb-phy@1a0c4800 {
775 #phy-cells = <1>;
777 clock-names = "ref";
780 u3port0: usb-phy@1a0c4900 {
782 #phy-cells = <1>;
784 clock-names = "ref";
787 u2port1: usb-phy@1a0c5000 {
789 #phy-cells = <1>;
791 clock-names = "ref";
796 compatible = "mediatek,mt7622-pciesys",
799 #clock-cells = <1>;
800 #reset-cells = <1>;
804 compatible = "mediatek,generic-pciecfg", "syscon";
809 compatible = "mediatek,mt7622-pcie";
812 reg-names = "port0";
813 linux,pci-domain = <0>;
814 #address-cells = <3>;
815 #size-cells = <2>;
817 interrupt-names = "pcie_irq";
824 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
827 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
828 bus-range = <0x00 0xff>;
832 #interrupt-cells = <1>;
833 interrupt-map-mask = <0 0 0 7>;
834 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
838 pcie_intc0: interrupt-controller {
839 interrupt-controller;
840 #address-cells = <0>;
841 #interrupt-cells = <1>;
846 compatible = "mediatek,mt7622-pcie";
849 reg-names = "port1";
850 linux,pci-domain = <1>;
851 #address-cells = <3>;
852 #size-cells = <2>;
854 interrupt-names = "pcie_irq";
862 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
865 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
866 bus-range = <0x00 0xff>;
870 #interrupt-cells = <1>;
871 interrupt-map-mask = <0 0 0 7>;
872 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
876 pcie_intc1: interrupt-controller {
877 interrupt-controller;
878 #address-cells = <0>;
879 #interrupt-cells = <1>;
884 compatible = "mediatek,mt7622-ahci",
885 "mediatek,mtk-ahci";
888 interrupt-names = "hostc";
894 clock-names = "ahb", "axi", "asic", "rbc", "pm";
896 phy-names = "sata-phy";
897 ports-implemented = <0x1>;
898 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
902 reset-names = "axi", "sw", "reg";
903 mediatek,phy-mode = <&pciesys>;
907 sata_phy: t-phy@1a243000 {
908 compatible = "mediatek,mt7622-tphy",
909 "mediatek,generic-tphy-v1";
910 #address-cells = <2>;
911 #size-cells = <2>;
915 sata_port: sata-phy@1a243000 {
918 clock-names = "ref";
919 #phy-cells = <1>;
924 compatible = "mediatek,mt7622-hifsys", "syscon";
929 compatible = "mediatek,mt7622-ethsys",
932 #clock-cells = <1>;
933 #reset-cells = <1>;
936 hsdma: dma-controller@1b007000 {
937 compatible = "mediatek,mt7622-hsdma";
941 clock-names = "hsdma";
942 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
943 #dma-cells = <1>;
944 dma-requests = <3>;
947 pcie_mirror: pcie-mirror@10000400 {
948 compatible = "mediatek,mt7622-pcie-mirror",
954 compatible = "mediatek,mt7622-wed",
961 compatible = "mediatek,mt7622-wed",
968 compatible = "mediatek,mt7622-eth",
969 "mediatek,mt2701-eth",
986 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
990 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
991 mediatek,ethsys = <ðsys>;
992 mediatek,sgmiisys = <&sgmiisys>;
993 cci-control-port = <&cci_control2>;
994 mediatek,wed = <&wed0>, <&wed1>;
995 mediatek,pcie-mirror = <&pcie_mirror>;
996 mediatek,hifsys = <&hifsys>;
997 dma-coherent;
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "mediatek,mt7622-sgmiisys",
1007 #clock-cells = <1>;