Lines Matching +full:0 +full:x1020f000

69 		#size-cells = <0>;
71 		cpu0: cpu@0 {
74 			reg = <0x0 0x0>;
89 			reg = <0x0 0x1>;
110 		#clock-cells = <0>;
115 		#clock-cells = <0>;
139 			reg = <0 0x43000000 0 0x30000>;
149 			thermal-sensors = <&thermal 0>;
215 		reg = <0 0x10000000 0 0x1000>;
222 		reg = <0 0x10001000 0 0x250>;
235 		reg = <0 0x10002000 0 0x1000>;
244 		reg = <0 0x10006000 0 0x1000>;
256 		reg = <0 0x10009000 0 0x1000>;
270 		reg = <0 0x10200620 0 0x20>;
276 		reg = <0 0x10206000 0 0x1000>;
281 			reg = <0x198 0xc>;
288 		reg = <0 0x10209000 0 0x1000>;
295 		reg = <0 0x10210000 0 0x1000>;
302 		reg = <0 0x1020f000 0 0x1000>;
309 		reg = <0 0x10211000 0 0x1000>,
310 		      <0 0x10005000 0 0x1000>;
314 		gpio-ranges = <&pio 0 0 103>;
324 		reg = <0 0x10212000 0 0x800>;
330 		reg = <0 0x10212800 0 0x200>;
341 		reg = <0 0x10310000 0 0x1000>,
342 		      <0 0x10320000 0 0x1000>,
343 		      <0 0x10340000 0 0x2000>,
344 		      <0 0x10360000 0 0x2000>;
351 		reg = <0 0x10390000 0 0x1000>;
352 		ranges = <0 0 0x10390000 0x10000>;
357 			reg = <0x1000 0x1000>;
363 			reg = <0x4000 0x1000>;
369 			reg = <0x5000 0x1000>;
374 			reg = <0x9000 0x5000>;
385 		reg = <0 0x11001000 0 0x1000>;
394 		reg = <0 0x11002000 0 0x400>;
405 		reg = <0 0x11003000 0 0x400>;
416 		reg = <0 0x11004000 0 0x400>;
427 		reg = <0 0x11005000 0 0x400>;
437 		reg = <0 0x11006000 0 0x1000>;
454 		reg = <0 0x11007000 0 0x90>,
455 		      <0 0x11000100 0 0x80>;
462 		#size-cells = <0>;
468 		reg = <0 0x11008000 0 0x90>,
469 		      <0 0x11000180 0 0x80>;
476 		#size-cells = <0>;
482 		reg = <0 0x11009000 0 0x90>,
483 		      <0 0x11000200 0 0x80>;
490 		#size-cells = <0>;
496 		reg = <0 0x1100a000 0 0x100>;
503 		#size-cells = <0>;
510 		reg = <0 0x1100b000 0 0x1000>;
511 		interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
526 		reg = <0 0x1100c000 0 0x1000>;
544 		reg = <0 0x1100D000 0 0x1000>;
551 		#size-cells = <0>;
557 		reg = <0 0x1100d000 0 0x1000>;
563 		#size-cells = <0>;
569 		reg = <0 0x1100e000 0 0x1000>;
579 		reg = <0 0x11014000 0 0xe0>;
584 		#size-cells = <0>;
590 		reg = <0 0x11016000 0 0x100>;
597 		#size-cells = <0>;
604 		reg = <0 0x11019000 0 0x400>;
614 		reg = <0 0x11220000 0 0x2000>;
697 			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
703 		reg = <0 0x11230000 0 0x1000>;
715 		reg = <0 0x11240000 0 0x1000>;
727 		reg = <0 0x18000000 0 0x100000>;
739 		reg = <0 0x1a000000 0 0x1000>;
747 		reg = <0 0x1a0c0000 0 0x01000>,
748 		      <0 0x1a0c4700 0 0x0100>;
767 		reg = <0 0x1a0c4000 0 0x700>;
774 			reg = <0 0x1a0c4800 0 0x0100>;
781 			reg = <0 0x1a0c4900 0 0x0700>;
788 			reg = <0 0x1a0c5000 0 0x0100>;
798 		reg = <0 0x1a100800 0 0x1000>;
805 		reg = <0 0x1a140000 0 0x1000>;
811 		reg = <0 0x1a143000 0 0x1000>;
813 		linux,pci-domain = <0>;
828 		bus-range = <0x00 0xff>;
829 		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
833 		interrupt-map-mask = <0 0 0 7>;
834 		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
835 				<0 0 0 2 &pcie_intc0 1>,
836 				<0 0 0 3 &pcie_intc0 2>,
837 				<0 0 0 4 &pcie_intc0 3>;
840 			#address-cells = <0>;
848 		reg = <0 0x1a145000 0 0x1000>;
866 		bus-range = <0x00 0xff>;
867 		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
871 		interrupt-map-mask = <0 0 0 7>;
872 		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
873 				<0 0 0 2 &pcie_intc1 1>,
874 				<0 0 0 3 &pcie_intc1 2>,
875 				<0 0 0 4 &pcie_intc1 3>;
878 			#address-cells = <0>;
886 		reg = <0 0x1a200000 0 0x1100>;
897 		ports-implemented = <0x1>;
916 			reg = <0 0x1a243000 0 0x0100>;
925 		reg = <0 0x1af00000 0 0x70>;
931 		reg = <0 0x1b000000 0 0x1000>;
938 		reg = <0 0x1b007000 0 0x1000>;
950 		reg = <0 0x10000400 0 0x10>;
956 		reg = <0 0x1020a000 0 0x1000>;
963 		reg = <0 0x1020b000 0 0x1000>;
971 		reg = <0 0x1b100000 0 0x20000>;
999 		#size-cells = <0>;
1006 		reg = <0 0x1b128000 0 0x3000>;