Lines Matching +full:pio +full:- +full:pins
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
41 gpio-keys {
42 compatible = "gpio-keys";
44 factory-key {
47 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
50 wps-key {
53 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
58 compatible = "gpio-leds";
60 led-0 {
61 label = "bpi-r64:pio:green";
63 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
64 default-state = "off";
67 led-1 {
68 label = "bpi-r64:pio:red";
70 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
71 default-state = "off";
79 reg_1p8v: regulator-1p8v {
80 compatible = "regulator-fixed";
81 regulator-name = "fixed-1.8V";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
84 regulator-always-on;
87 reg_3p3v: regulator-3p3v {
88 compatible = "regulator-fixed";
89 regulator-name = "fixed-3.3V";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-boot-on;
93 regulator-always-on;
96 reg_5v: regulator-5v {
97 compatible = "regulator-fixed";
98 regulator-name = "fixed-5V";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
101 regulator-boot-on;
102 regulator-always-on;
115 pinctrl-names = "default";
116 pinctrl-0 = <&irrx_pins>;
123 compatible = "mediatek,eth-mac";
125 phy-mode = "2500base-x";
127 fixed-link {
129 full-duplex;
135 compatible = "mediatek,eth-mac";
137 phy-mode = "rgmii";
139 fixed-link {
141 full-duplex;
146 mdio: mdio-bus {
147 #address-cells = <1>;
148 #size-cells = <0>;
153 reset-gpios = <&pio 54 0>;
156 #address-cells = <1>;
157 #size-cells = <0>;
188 phy-mode = "2500base-x";
190 fixed-link {
192 full-duplex;
203 pinctrl-names = "default";
204 pinctrl-0 = <&i2c1_pins>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&i2c2_pins>;
215 pinctrl-names = "default", "state_uhs";
216 pinctrl-0 = <&emmc_pins_default>;
217 pinctrl-1 = <&emmc_pins_uhs>;
219 bus-width = <8>;
220 max-frequency = <50000000>;
221 cap-mmc-highspeed;
222 mmc-hs200-1_8v;
223 vmmc-supply = <®_3p3v>;
224 vqmmc-supply = <®_1p8v>;
225 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
226 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
227 non-removable;
231 pinctrl-names = "default", "state_uhs";
232 pinctrl-0 = <&sd0_pins_default>;
233 pinctrl-1 = <&sd0_pins_uhs>;
235 bus-width = <4>;
236 max-frequency = <50000000>;
237 cap-sd-highspeed;
239 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
240 vmmc-supply = <®_3p3v>;
241 vqmmc-supply = <®_3p3v>;
242 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
243 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
247 pinctrl-names = "default";
248 pinctrl-0 = <¶llel_nand_pins>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&spi_nor_pins>;
258 compatible = "jedec,spi-nor";
264 pinctrl-names = "default";
265 pinctrl-0 = <&pcie0_pins>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pcie1_pins>;
275 &pio {
277 * SATA functions. i.e. output-high: PCIe, output-low: SATA
280 gpio-hog;
282 output-high;
286 emmc_pins_default: emmc-pins-default {
293 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
296 conf-cmd-dat {
297 pins = "NDL0", "NDL1", "NDL2",
300 input-enable;
301 bias-pull-up;
304 conf-clk {
305 pins = "NCLE";
306 bias-pull-down;
310 emmc_pins_uhs: emmc-pins-uhs {
316 conf-cmd-dat {
317 pins = "NDL0", "NDL1", "NDL2",
320 input-enable;
321 drive-strength = <4>;
322 bias-pull-up;
325 conf-clk {
326 pins = "NCLE";
327 drive-strength = <4>;
328 bias-pull-down;
332 eth_pins: eth-pins {
339 i2c1_pins: i2c1-pins {
346 i2c2_pins: i2c2-pins {
353 i2s1_pins: i2s1-pins {
362 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
364 drive-strength = <12>;
365 bias-pull-down;
369 irrx_pins: irrx-pins {
376 irtx_pins: irtx-pins {
384 parallel_nand_pins: parallel-nand-pins {
391 pcie0_pins: pcie0-pins {
400 pcie1_pins: pcie1-pins {
409 pmic_bus_pins: pmic-bus-pins {
416 pwm_pins: pwm-pins {
428 wled_pins: wled-pins {
435 sd0_pins_default: sd0-pins-default {
445 conf-cmd-data {
446 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
448 input-enable;
449 drive-strength = <8>;
450 bias-pull-up;
452 conf-clk {
453 pins = "I2S3_OUT";
454 drive-strength = <12>;
455 bias-pull-down;
457 conf-cd {
458 pins = "TXD3";
459 bias-pull-up;
463 sd0_pins_uhs: sd0-pins-uhs {
469 conf-cmd-data {
470 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
472 input-enable;
473 bias-pull-up;
476 conf-clk {
477 pins = "I2S3_OUT";
478 bias-pull-down;
482 /* Serial NAND is shared pin with SPI-NOR */
483 serial_nand_pins: serial-nand-pins {
490 spic0_pins: spic0-pins {
497 spic1_pins: spic1-pins {
504 /* SPI-NOR is shared pin with serial NAND */
505 spi_nor_pins: spi-nor-pins {
512 /* serial NAND is shared pin with SPI-NOR */
513 serial_nand_pins: serial-nand-pins {
520 uart0_pins: uart0-pins {
527 uart2_pins: uart2-pins {
534 watchdog_pins: watchdog-pins {
543 pinctrl-names = "default";
544 pinctrl-0 = <&pwm_pins>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&pmic_bus_pins>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&spic0_pins>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&spic1_pins>;
575 vusb33-supply = <®_3p3v>;
576 vbus-supply = <®_5v>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&uart0_pins>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&uart2_pins>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&watchdog_pins>;