Lines Matching +full:0 +full:x580000
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
60 CP11X_LABEL(ethernet): ethernet@0 {
62 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
86 port-id = <0>;
87 gop-port-id = <0>;
132 reg = <0x120000 0x6000>;
138 #size-cells = <0>;
140 CP11X_LABEL(comphy0): phy@0 {
141 reg = <0>;
173 #size-cells = <0>;
175 reg = <0x12a200 0x10>;
183 #size-cells = <0>;
185 reg = <0x12a600 0x10>;
193 reg = <0x1e0000 0x440>;
199 reg = <0x10 0x20>;
207 reg = <0x50 0x10>;
216 reg = <0x284000 0x20>, <0x284080 0x24>;
223 reg = <0x440000 0x2000>;
232 offset = <0x100>;
236 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
237 marvell,pwm-offset = <0x1f0>;
253 offset = <0x140>;
257 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
258 marvell,pwm-offset = <0x1f0>;
275 reg = <0x400000 0x1000>;
281 reg = <0x70 0x10>;
290 reg = <0x580000 0x2000>;
293 #size-cells = <0>;
296 CP11X_LABEL(utmi0): usb-phy@0 {
297 reg = <0>;
298 #phy-cells = <0>;
303 #phy-cells = <0>;
310 reg = <0x500000 0x4000>;
322 reg = <0x510000 0x4000>;
334 reg = <0x540000 0x30000>;
340 #size-cells = <0>;
343 sata-port@0 {
344 reg = <0>;
354 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
364 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
374 reg = <0x700600 0x50>;
375 #address-cells = <0x1>;
376 #size-cells = <0x0>;
385 reg = <0x700680 0x50>;
387 #size-cells = <0>;
396 reg = <0x701000 0x20>;
398 #size-cells = <0>;
408 reg = <0x701100 0x20>;
410 #size-cells = <0>;
420 reg = <0x702000 0x100>;
432 reg = <0x702100 0x100>;
444 reg = <0x702200 0x100>;
456 reg = <0x702300 0x100>;
474 reg = <0x720000 0x54>;
476 #size-cells = <0>;
488 reg = <0x760000 0x7d>;
498 reg = <0x780000 0x300>;
508 reg = <0x800000 0x200000>;
526 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
527 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
536 bus-range = <0 0xff>;
538 …ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0…
539 interrupt-map-mask = <0 0 0 0>;
540 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
550 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
551 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
560 bus-range = <0 0xff>;
562 …ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1…
563 interrupt-map-mask = <0 0 0 0>;
564 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
575 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
576 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
585 bus-range = <0 0xff>;
587 …ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2…
588 interrupt-map-mask = <0 0 0 0>;
589 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;