Lines Matching +full:thermal +full:- +full:sensors
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
36 * mainline U-Boot, and should be updated by the
40 psci-area@4000000 {
42 no-map;
47 #address-cells = <2>;
48 #size-cells = <2>;
49 compatible = "simple-bus";
50 interrupt-parent = <&gic>;
53 config-space@f0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "simple-bus";
60 compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
62 dma-coherent;
63 #iommu-cells = <1>;
64 #global-interrupts = <1>;
77 gic: interrupt-controller@210000 {
78 compatible = "arm,gic-400";
79 #interrupt-cells = <3>;
80 #address-cells = <1>;
81 #size-cells = <1>;
83 interrupt-controller;
91 compatible = "arm,gic-v2m-frame";
92 msi-controller;
94 arm,msi-base-spi = <160>;
95 arm,msi-num-spis = <32>;
98 compatible = "arm,gic-v2m-frame";
99 msi-controller;
101 arm,msi-base-spi = <192>;
102 arm,msi-num-spis = <32>;
105 compatible = "arm,gic-v2m-frame";
106 msi-controller;
108 arm,msi-base-spi = <224>;
109 arm,msi-num-spis = <32>;
112 compatible = "arm,gic-v2m-frame";
113 msi-controller;
115 arm,msi-base-spi = <256>;
116 arm,msi-num-spis = <32>;
121 compatible = "arm,armv8-timer";
129 compatible = "arm,cortex-a72-pmu";
130 interrupt-parent = <&pic>;
135 compatible = "marvell,odmi-controller";
136 interrupt-controller;
137 msi-controller;
138 marvell,odmi-frames = <4>;
143 marvell,spi-base = <128>, <136>, <144>, <152>;
147 compatible = "marvell,ap806-gicp";
149 marvell,spi-ranges = <64 64>, <288 64>;
150 msi-controller;
153 pic: interrupt-controller@3f0100 {
154 compatible = "marvell,armada-8k-pic";
156 #interrupt-cells = <1>;
157 interrupt-controller;
161 sei: interrupt-controller@3f0200 {
162 compatible = "marvell,ap806-sei";
165 #interrupt-cells = <1>;
166 interrupt-controller;
167 msi-controller;
171 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
174 msi-parent = <&gic_v2m0>;
176 dma-coherent;
180 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
183 msi-parent = <&gic_v2m0>;
185 dma-coherent;
189 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
192 msi-parent = <&gic_v2m0>;
194 dma-coherent;
198 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
201 msi-parent = <&gic_v2m0>;
203 dma-coherent;
207 compatible = "marvell,armada-380-spi";
209 #address-cells = <1>;
210 #size-cells = <0>;
217 compatible = "marvell,mv78230-i2c";
219 #address-cells = <1>;
220 #size-cells = <0>;
227 compatible = "snps,dw-apb-uart";
229 reg-shift = <2>;
231 reg-io-width = <1>;
237 compatible = "snps,dw-apb-uart";
239 reg-shift = <2>;
241 reg-io-width = <1>;
248 compatible = "arm,sbsa-gwdt";
254 compatible = "marvell,armada-ap806-sdhci";
257 clock-names = "core";
259 dma-coherent;
260 marvell,xenon-phy-slow-mode;
264 ap_syscon0: system-controller@6f4000 {
265 compatible = "syscon", "simple-mfd";
269 compatible = "marvell,ap806-pinctrl";
271 uart0_pins: uart0-pins {
278 compatible = "marvell,armada-8k-gpio";
281 gpio-controller;
282 #gpio-cells = <2>;
283 gpio-ranges = <&ap_pinctrl 0 0 20>;
284 marvell,pwm-offset = <0x10c0>;
285 #pwm-cells = <2>;
290 ap_syscon1: system-controller@6f8000 {
291 compatible = "syscon", "simple-mfd";
293 #address-cells = <1>;
294 #size-cells = <1>;
296 ap_thermal: thermal-sensor@80 {
297 compatible = "marvell,armada-ap806-thermal";
299 interrupt-parent = <&sei>;
301 #thermal-sensor-cells = <1>;
308 * The thermal IP features one internal sensor plus, if applicable, one
311 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
314 thermal-zones {
315 ap_thermal_ic: ap-thermal-ic {
316 polling-delay-passive = <0>; /* Interrupt driven */
317 polling-delay = <0>; /* Interrupt driven */
319 thermal-sensors = <&ap_thermal 0>;
322 ap_crit: ap-crit {
329 cooling-maps { };
332 ap_thermal_cpu0: ap-thermal-cpu0 {
333 polling-delay-passive = <1000>;
334 polling-delay = <1000>;
336 thermal-sensors = <&ap_thermal 1>;
339 cpu0_hot: cpu0-hot {
344 cpu0_emerg: cpu0-emerg {
351 cooling-maps {
352 map0_hot: map0-hot {
354 cooling-device = <&cpu0 1 2>,
357 map0_emerg: map0-ermerg {
359 cooling-device = <&cpu0 3 3>,
365 ap_thermal_cpu1: ap-thermal-cpu1 {
366 polling-delay-passive = <1000>;
367 polling-delay = <1000>;
369 thermal-sensors = <&ap_thermal 2>;
372 cpu1_hot: cpu1-hot {
377 cpu1_emerg: cpu1-emerg {
384 cooling-maps {
385 map1_hot: map1-hot {
387 cooling-device = <&cpu0 1 2>,
390 map1_emerg: map1-emerg {
392 cooling-device = <&cpu0 3 3>,
398 ap_thermal_cpu2: ap-thermal-cpu2 {
399 polling-delay-passive = <1000>;
400 polling-delay = <1000>;
402 thermal-sensors = <&ap_thermal 3>;
405 cpu2_hot: cpu2-hot {
410 cpu2_emerg: cpu2-emerg {
417 cooling-maps {
418 map2_hot: map2-hot {
420 cooling-device = <&cpu2 1 2>,
423 map2_emerg: map2-emerg {
425 cooling-device = <&cpu2 3 3>,
431 ap_thermal_cpu3: ap-thermal-cpu3 {
432 polling-delay-passive = <1000>;
433 polling-delay = <1000>;
435 thermal-sensors = <&ap_thermal 4>;
438 cpu3_hot: cpu3-hot {
443 cpu3_emerg: cpu3-emerg {
450 cooling-maps {
451 map3_hot: map3-bhot {
453 cooling-device = <&cpu2 1 2>,
456 map3_emerg: map3-emerg {
458 cooling-device = <&cpu2 3 3>,