Lines Matching +full:0 +full:xb0000
35 reg = <0 0x4000000 0 0x200000>;
42 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0>;
80 /* 32M internal register @ 0xd000_0000 */
81 ranges = <0x0 0x0 0xd0000000 0x2000000>;
85 reg = <0x8300 0x40>;
93 reg = <0xd000 0x1000>;
99 #size-cells = <0>;
100 reg = <0x10600 0xA00>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
109 reg = <0x11000 0x24>;
111 #size-cells = <0>;
120 reg = <0x11080 0x24>;
122 #size-cells = <0>;
132 reg = <0x11500 0x40>;
137 reg = <0x12010 0x4>, <0x12210 0x4>;
138 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
147 reg = <0x12000 0x18>;
148 clocks = <&uartclk 0>;
159 reg = <0x12200 0x30>;
171 reg = <0x13000 0x100>;
172 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
179 reg = <0x18000 0x100>;
180 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
187 reg = <0x13200 0x100>;
195 reg = <0x13800 0x100>, <0x13C00 0x20>;
196 /* MPP1[19:0] */
199 gpio-ranges = <&pinctrl_nb 0 0 36>;
221 #clock-cells = <0>;
263 reg = <0x14000 0x60>;
268 reg = <0x18300 0x300>,
269 <0x1F000 0x400>,
270 <0x5C000 0x400>,
271 <0xe0178 0x8>;
277 #size-cells = <0>;
281 comphy0: phy@0 {
282 reg = <0>;
300 reg = <0x18800 0x100>, <0x18C00 0x20>;
301 /* MPP2[23:0] */
304 gpio-ranges = <&pinctrl_sb 0 0 30>;
344 reg = <0x30000 0x4000>;
352 #size-cells = <0>;
354 reg = <0x32004 0x4>;
359 reg = <0x40000 0x4000>;
368 reg = <0x58000 0x4000>;
372 phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
379 reg = <0x5d000 0x800>;
381 #phy-cells = <0>;
387 reg = <0x5d800 0x800>;
392 reg = <0x5e000 0x1000>;
402 reg = <0x5f000 0x800>;
404 #phy-cells = <0>;
410 reg = <0x5f800 0x800>;
415 reg = <0x60900 0x100>,
416 <0x60b00 0x100>;
428 reg = <0x90000 0x20000>;
442 reg = <0xb0000 0x100>;
450 reg = <0xd0000 0x300>,
451 <0x1e808 0x4>;
453 clocks = <&nb_periph_clk 0>;
461 reg = <0xd8000 0x300>,
462 <0x17808 0x4>;
464 clocks = <&nb_periph_clk 0>;
471 reg = <0xe0000 0x178>;
474 phys = <&comphy2 0>;
483 reg = <0x1d00000 0x10000>, /* GICD */
484 <0x1d40000 0x40000>, /* GICR */
485 <0x1d80000 0x2000>, /* GICC */
486 <0x1d90000 0x2000>, /* GICH */
487 <0x1da0000 0x20000>; /* GICV */
496 reg = <0 0xd0070000 0 0x20000>;
499 bus-range = <0x00 0xff>;
506 * The 128 MiB address range [0xe8000000-0xf0000000] is
512 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
513 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
514 interrupt-map-mask = <0 0 0 7>;
515 interrupt-map = <0 0 0 1 &pcie_intc 0>,
516 <0 0 0 2 &pcie_intc 1>,
517 <0 0 0 3 &pcie_intc 2>,
518 <0 0 0 4 &pcie_intc 3>;
520 phys = <&comphy1 0>;
531 mboxes = <&rwtm 0>;