Lines Matching +full:0 +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
269 compatible = "arm,cortex-a72";
270 reg = <0x10000>;
271 enable-method = "psci";
272 next-level-cache = <&cluster0_l2>;
273 numa-node-id = <0>;
278 compatible = "arm,cortex-a72";
279 reg = <0x10001>;
280 enable-method = "psci";
281 next-level-cache = <&cluster0_l2>;
282 numa-node-id = <0>;
287 compatible = "arm,cortex-a72";
288 reg = <0x10002>;
289 enable-method = "psci";
290 next-level-cache = <&cluster0_l2>;
291 numa-node-id = <0>;
296 compatible = "arm,cortex-a72";
297 reg = <0x10003>;
298 enable-method = "psci";
299 next-level-cache = <&cluster0_l2>;
300 numa-node-id = <0>;
305 compatible = "arm,cortex-a72";
306 reg = <0x10100>;
307 enable-method = "psci";
308 next-level-cache = <&cluster1_l2>;
309 numa-node-id = <0>;
314 compatible = "arm,cortex-a72";
315 reg = <0x10101>;
316 enable-method = "psci";
317 next-level-cache = <&cluster1_l2>;
318 numa-node-id = <0>;
323 compatible = "arm,cortex-a72";
324 reg = <0x10102>;
325 enable-method = "psci";
326 next-level-cache = <&cluster1_l2>;
327 numa-node-id = <0>;
332 compatible = "arm,cortex-a72";
333 reg = <0x10103>;
334 enable-method = "psci";
335 next-level-cache = <&cluster1_l2>;
336 numa-node-id = <0>;
341 compatible = "arm,cortex-a72";
342 reg = <0x10200>;
343 enable-method = "psci";
344 next-level-cache = <&cluster2_l2>;
345 numa-node-id = <0>;
350 compatible = "arm,cortex-a72";
351 reg = <0x10201>;
352 enable-method = "psci";
353 next-level-cache = <&cluster2_l2>;
354 numa-node-id = <0>;
359 compatible = "arm,cortex-a72";
360 reg = <0x10202>;
361 enable-method = "psci";
362 next-level-cache = <&cluster2_l2>;
363 numa-node-id = <0>;
368 compatible = "arm,cortex-a72";
369 reg = <0x10203>;
370 enable-method = "psci";
371 next-level-cache = <&cluster2_l2>;
372 numa-node-id = <0>;
377 compatible = "arm,cortex-a72";
378 reg = <0x10300>;
379 enable-method = "psci";
380 next-level-cache = <&cluster3_l2>;
381 numa-node-id = <0>;
386 compatible = "arm,cortex-a72";
387 reg = <0x10301>;
388 enable-method = "psci";
389 next-level-cache = <&cluster3_l2>;
390 numa-node-id = <0>;
395 compatible = "arm,cortex-a72";
396 reg = <0x10302>;
397 enable-method = "psci";
398 next-level-cache = <&cluster3_l2>;
399 numa-node-id = <0>;
404 compatible = "arm,cortex-a72";
405 reg = <0x10303>;
406 enable-method = "psci";
407 next-level-cache = <&cluster3_l2>;
408 numa-node-id = <0>;
413 compatible = "arm,cortex-a72";
414 reg = <0x30000>;
415 enable-method = "psci";
416 next-level-cache = <&cluster4_l2>;
417 numa-node-id = <1>;
422 compatible = "arm,cortex-a72";
423 reg = <0x30001>;
424 enable-method = "psci";
425 next-level-cache = <&cluster4_l2>;
426 numa-node-id = <1>;
431 compatible = "arm,cortex-a72";
432 reg = <0x30002>;
433 enable-method = "psci";
434 next-level-cache = <&cluster4_l2>;
435 numa-node-id = <1>;
440 compatible = "arm,cortex-a72";
441 reg = <0x30003>;
442 enable-method = "psci";
443 next-level-cache = <&cluster4_l2>;
444 numa-node-id = <1>;
449 compatible = "arm,cortex-a72";
450 reg = <0x30100>;
451 enable-method = "psci";
452 next-level-cache = <&cluster5_l2>;
453 numa-node-id = <1>;
458 compatible = "arm,cortex-a72";
459 reg = <0x30101>;
460 enable-method = "psci";
461 next-level-cache = <&cluster5_l2>;
462 numa-node-id = <1>;
467 compatible = "arm,cortex-a72";
468 reg = <0x30102>;
469 enable-method = "psci";
470 next-level-cache = <&cluster5_l2>;
471 numa-node-id = <1>;
476 compatible = "arm,cortex-a72";
477 reg = <0x30103>;
478 enable-method = "psci";
479 next-level-cache = <&cluster5_l2>;
480 numa-node-id = <1>;
485 compatible = "arm,cortex-a72";
486 reg = <0x30200>;
487 enable-method = "psci";
488 next-level-cache = <&cluster6_l2>;
489 numa-node-id = <1>;
494 compatible = "arm,cortex-a72";
495 reg = <0x30201>;
496 enable-method = "psci";
497 next-level-cache = <&cluster6_l2>;
498 numa-node-id = <1>;
503 compatible = "arm,cortex-a72";
504 reg = <0x30202>;
505 enable-method = "psci";
506 next-level-cache = <&cluster6_l2>;
507 numa-node-id = <1>;
512 compatible = "arm,cortex-a72";
513 reg = <0x30203>;
514 enable-method = "psci";
515 next-level-cache = <&cluster6_l2>;
516 numa-node-id = <1>;
521 compatible = "arm,cortex-a72";
522 reg = <0x30300>;
523 enable-method = "psci";
524 next-level-cache = <&cluster7_l2>;
525 numa-node-id = <1>;
530 compatible = "arm,cortex-a72";
531 reg = <0x30301>;
532 enable-method = "psci";
533 next-level-cache = <&cluster7_l2>;
534 numa-node-id = <1>;
539 compatible = "arm,cortex-a72";
540 reg = <0x30302>;
541 enable-method = "psci";
542 next-level-cache = <&cluster7_l2>;
543 numa-node-id = <1>;
548 compatible = "arm,cortex-a72";
549 reg = <0x30303>;
550 enable-method = "psci";
551 next-level-cache = <&cluster7_l2>;
552 numa-node-id = <1>;
557 compatible = "arm,cortex-a72";
558 reg = <0x50000>;
559 enable-method = "psci";
560 next-level-cache = <&cluster8_l2>;
561 numa-node-id = <2>;
566 compatible = "arm,cortex-a72";
567 reg = <0x50001>;
568 enable-method = "psci";
569 next-level-cache = <&cluster8_l2>;
570 numa-node-id = <2>;
575 compatible = "arm,cortex-a72";
576 reg = <0x50002>;
577 enable-method = "psci";
578 next-level-cache = <&cluster8_l2>;
579 numa-node-id = <2>;
584 compatible = "arm,cortex-a72";
585 reg = <0x50003>;
586 enable-method = "psci";
587 next-level-cache = <&cluster8_l2>;
588 numa-node-id = <2>;
593 compatible = "arm,cortex-a72";
594 reg = <0x50100>;
595 enable-method = "psci";
596 next-level-cache = <&cluster9_l2>;
597 numa-node-id = <2>;
602 compatible = "arm,cortex-a72";
603 reg = <0x50101>;
604 enable-method = "psci";
605 next-level-cache = <&cluster9_l2>;
606 numa-node-id = <2>;
611 compatible = "arm,cortex-a72";
612 reg = <0x50102>;
613 enable-method = "psci";
614 next-level-cache = <&cluster9_l2>;
615 numa-node-id = <2>;
620 compatible = "arm,cortex-a72";
621 reg = <0x50103>;
622 enable-method = "psci";
623 next-level-cache = <&cluster9_l2>;
624 numa-node-id = <2>;
629 compatible = "arm,cortex-a72";
630 reg = <0x50200>;
631 enable-method = "psci";
632 next-level-cache = <&cluster10_l2>;
633 numa-node-id = <2>;
638 compatible = "arm,cortex-a72";
639 reg = <0x50201>;
640 enable-method = "psci";
641 next-level-cache = <&cluster10_l2>;
642 numa-node-id = <2>;
647 compatible = "arm,cortex-a72";
648 reg = <0x50202>;
649 enable-method = "psci";
650 next-level-cache = <&cluster10_l2>;
651 numa-node-id = <2>;
656 compatible = "arm,cortex-a72";
657 reg = <0x50203>;
658 enable-method = "psci";
659 next-level-cache = <&cluster10_l2>;
660 numa-node-id = <2>;
665 compatible = "arm,cortex-a72";
666 reg = <0x50300>;
667 enable-method = "psci";
668 next-level-cache = <&cluster11_l2>;
669 numa-node-id = <2>;
674 compatible = "arm,cortex-a72";
675 reg = <0x50301>;
676 enable-method = "psci";
677 next-level-cache = <&cluster11_l2>;
678 numa-node-id = <2>;
683 compatible = "arm,cortex-a72";
684 reg = <0x50302>;
685 enable-method = "psci";
686 next-level-cache = <&cluster11_l2>;
687 numa-node-id = <2>;
692 compatible = "arm,cortex-a72";
693 reg = <0x50303>;
694 enable-method = "psci";
695 next-level-cache = <&cluster11_l2>;
696 numa-node-id = <2>;
701 compatible = "arm,cortex-a72";
702 reg = <0x70000>;
703 enable-method = "psci";
704 next-level-cache = <&cluster12_l2>;
705 numa-node-id = <3>;
710 compatible = "arm,cortex-a72";
711 reg = <0x70001>;
712 enable-method = "psci";
713 next-level-cache = <&cluster12_l2>;
714 numa-node-id = <3>;
719 compatible = "arm,cortex-a72";
720 reg = <0x70002>;
721 enable-method = "psci";
722 next-level-cache = <&cluster12_l2>;
723 numa-node-id = <3>;
728 compatible = "arm,cortex-a72";
729 reg = <0x70003>;
730 enable-method = "psci";
731 next-level-cache = <&cluster12_l2>;
732 numa-node-id = <3>;
737 compatible = "arm,cortex-a72";
738 reg = <0x70100>;
739 enable-method = "psci";
740 next-level-cache = <&cluster13_l2>;
741 numa-node-id = <3>;
746 compatible = "arm,cortex-a72";
747 reg = <0x70101>;
748 enable-method = "psci";
749 next-level-cache = <&cluster13_l2>;
750 numa-node-id = <3>;
755 compatible = "arm,cortex-a72";
756 reg = <0x70102>;
757 enable-method = "psci";
758 next-level-cache = <&cluster13_l2>;
759 numa-node-id = <3>;
764 compatible = "arm,cortex-a72";
765 reg = <0x70103>;
766 enable-method = "psci";
767 next-level-cache = <&cluster13_l2>;
768 numa-node-id = <3>;
773 compatible = "arm,cortex-a72";
774 reg = <0x70200>;
775 enable-method = "psci";
776 next-level-cache = <&cluster14_l2>;
777 numa-node-id = <3>;
782 compatible = "arm,cortex-a72";
783 reg = <0x70201>;
784 enable-method = "psci";
785 next-level-cache = <&cluster14_l2>;
786 numa-node-id = <3>;
791 compatible = "arm,cortex-a72";
792 reg = <0x70202>;
793 enable-method = "psci";
794 next-level-cache = <&cluster14_l2>;
795 numa-node-id = <3>;
800 compatible = "arm,cortex-a72";
801 reg = <0x70203>;
802 enable-method = "psci";
803 next-level-cache = <&cluster14_l2>;
804 numa-node-id = <3>;
809 compatible = "arm,cortex-a72";
810 reg = <0x70300>;
811 enable-method = "psci";
812 next-level-cache = <&cluster15_l2>;
813 numa-node-id = <3>;
818 compatible = "arm,cortex-a72";
819 reg = <0x70301>;
820 enable-method = "psci";
821 next-level-cache = <&cluster15_l2>;
822 numa-node-id = <3>;
827 compatible = "arm,cortex-a72";
828 reg = <0x70302>;
829 enable-method = "psci";
830 next-level-cache = <&cluster15_l2>;
831 numa-node-id = <3>;
836 compatible = "arm,cortex-a72";
837 reg = <0x70303>;
838 enable-method = "psci";
839 next-level-cache = <&cluster15_l2>;
840 numa-node-id = <3>;
843 cluster0_l2: l2-cache0 {
847 cluster1_l2: l2-cache1 {
851 cluster2_l2: l2-cache2 {
855 cluster3_l2: l2-cache3 {
859 cluster4_l2: l2-cache4 {
863 cluster5_l2: l2-cache5 {
867 cluster6_l2: l2-cache6 {
871 cluster7_l2: l2-cache7 {
875 cluster8_l2: l2-cache8 {
879 cluster9_l2: l2-cache9 {
883 cluster10_l2: l2-cache10 {
887 cluster11_l2: l2-cache11 {
891 cluster12_l2: l2-cache12 {
895 cluster13_l2: l2-cache13 {
899 cluster14_l2: l2-cache14 {
903 cluster15_l2: l2-cache15 {
908 gic: interrupt-controller@4d000000 {
909 compatible = "arm,gic-v3";
910 #interrupt-cells = <3>;
911 #address-cells = <2>;
912 #size-cells = <2>;
914 interrupt-controller;
915 #redistributor-regions = <4>;
916 redistributor-stride = <0x0 0x40000>;
917 reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */
918 <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */
919 <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */
920 <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */
921 <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */
922 <0x0 0xfe000000 0x0 0x10000>, /* GICC */
923 <0x0 0xfe010000 0x0 0x10000>, /* GICH */
924 <0x0 0xfe020000 0x0 0x10000>; /* GICV */
927 p0_its_peri_a: msi-controller@4c000000 {
928 compatible = "arm,gic-v3-its";
929 msi-controller;
930 #msi-cells = <1>;
931 reg = <0x0 0x4c000000 0x0 0x40000>;
934 p0_its_peri_b: msi-controller@6c000000 {
935 compatible = "arm,gic-v3-its";
936 msi-controller;
937 #msi-cells = <1>;
938 reg = <0x0 0x6c000000 0x0 0x40000>;
941 p0_its_dsa_a: msi-controller@c6000000 {
942 compatible = "arm,gic-v3-its";
943 msi-controller;
944 #msi-cells = <1>;
945 reg = <0x0 0xc6000000 0x0 0x40000>;
948 p0_its_dsa_b: msi-controller@8c6000000 {
949 compatible = "arm,gic-v3-its";
950 msi-controller;
951 #msi-cells = <1>;
952 reg = <0x8 0xc6000000 0x0 0x40000>;
955 p1_its_peri_a: msi-controller@4004c000000 {
956 compatible = "arm,gic-v3-its";
957 msi-controller;
958 #msi-cells = <1>;
959 reg = <0x400 0x4c000000 0x0 0x40000>;
962 p1_its_peri_b: msi-controller@4006c000000 {
963 compatible = "arm,gic-v3-its";
964 msi-controller;
965 #msi-cells = <1>;
966 reg = <0x400 0x6c000000 0x0 0x40000>;
969 p1_its_dsa_a: msi-controller@400c6000000 {
970 compatible = "arm,gic-v3-its";
971 msi-controller;
972 #msi-cells = <1>;
973 reg = <0x400 0xc6000000 0x0 0x40000>;
976 p1_its_dsa_b: msi-controller@408c6000000 {
977 compatible = "arm,gic-v3-its";
978 msi-controller;
979 #msi-cells = <1>;
980 reg = <0x408 0xc6000000 0x0 0x40000>;
985 compatible = "arm,armv8-timer";
993 compatible = "arm,cortex-a72-pmu";
997 p0_mbigen_peri_b: interrupt-controller@60080000 {
998 compatible = "hisilicon,mbigen-v2";
999 reg = <0x0 0x60080000 0x0 0x10000>;
1002 msi-parent = <&p0_its_peri_b 0x120c7>;
1003 interrupt-controller;
1004 #interrupt-cells = <2>;
1005 num-pins = <1>;
1009 p0_mbigen_pcie_a: interrupt-controller@a0080000 {
1010 compatible = "hisilicon,mbigen-v2";
1011 reg = <0x0 0xa0080000 0x0 0x10000>;
1014 msi-parent = <&p0_its_dsa_a 0x40087>;
1015 interrupt-controller;
1016 #interrupt-cells = <2>;
1017 num-pins = <10>;
1021 msi-parent = <&p0_its_dsa_a 0x40000>;
1022 interrupt-controller;
1023 #interrupt-cells = <2>;
1024 num-pins = <128>;
1028 msi-parent = <&p0_its_dsa_a 0x40040>;
1029 interrupt-controller;
1030 #interrupt-cells = <2>;
1031 num-pins = <128>;
1035 msi-parent = <&p0_its_dsa_a 0x40b0c>;
1036 interrupt-controller;
1037 #interrupt-cells = <2>;
1038 num-pins = <3>;
1042 msi-parent = <&p0_its_dsa_a 0x40080>;
1043 interrupt-controller;
1044 #interrupt-cells = <2>;
1045 num-pins = <2>;
1048 p0_mbigen_alg_a:interrupt-controller@d0080000 {
1049 compatible = "hisilicon,mbigen-v2";
1050 reg = <0x0 0xd0080000 0x0 0x10000>;
1053 msi-parent = <&p0_its_dsa_a 0x40400>;
1054 interrupt-controller;
1055 #interrupt-cells = <2>;
1056 num-pins = <33>;
1059 msi-parent = <&p0_its_dsa_a 0x40b1b>;
1060 interrupt-controller;
1061 #interrupt-cells = <2>;
1062 num-pins = <3>;
1065 p0_mbigen_alg_b:interrupt-controller@8,d0080000 {
1066 compatible = "hisilicon,mbigen-v2";
1067 reg = <0x8 0xd0080000 0x0 0x10000>;
1070 msi-parent = <&p0_its_dsa_b 0x42400>;
1071 interrupt-controller;
1072 #interrupt-cells = <2>;
1073 num-pins = <33>;
1076 msi-parent = <&p0_its_dsa_b 0x42b1b>;
1077 interrupt-controller;
1078 #interrupt-cells = <2>;
1079 num-pins = <3>;
1082 p1_mbigen_alg_a:interrupt-controller@400,d0080000 {
1083 compatible = "hisilicon,mbigen-v2";
1084 reg = <0x400 0xd0080000 0x0 0x10000>;
1087 msi-parent = <&p1_its_dsa_a 0x44400>;
1088 interrupt-controller;
1089 #interrupt-cells = <2>;
1090 num-pins = <33>;
1093 msi-parent = <&p1_its_dsa_a 0x44b1b>;
1094 interrupt-controller;
1095 #interrupt-cells = <2>;
1096 num-pins = <3>;
1099 p1_mbigen_alg_b:interrupt-controller@408,d0080000 {
1100 compatible = "hisilicon,mbigen-v2";
1101 reg = <0x408 0xd0080000 0x0 0x10000>;
1104 msi-parent = <&p1_its_dsa_b 0x46400>;
1105 interrupt-controller;
1106 #interrupt-cells = <2>;
1107 num-pins = <33>;
1110 msi-parent = <&p1_its_dsa_b 0x46b1b>;
1111 interrupt-controller;
1112 #interrupt-cells = <2>;
1113 num-pins = <3>;
1116 p0_mbigen_dsa_a: interrupt-controller@c0080000 {
1117 compatible = "hisilicon,mbigen-v2";
1118 reg = <0x0 0xc0080000 0x0 0x10000>;
1121 msi-parent = <&p0_its_dsa_a 0x40800>;
1122 interrupt-controller;
1123 #interrupt-cells = <2>;
1124 num-pins = <409>;
1127 mbigen_dsa_roce: intc-roce {
1128 msi-parent = <&p0_its_dsa_a 0x40B1E>;
1129 interrupt-controller;
1130 #interrupt-cells = <2>;
1131 num-pins = <34>;
1134 mbigen_sas0: intc-sas0 {
1135 msi-parent = <&p0_its_dsa_a 0x40900>;
1136 interrupt-controller;
1137 #interrupt-cells = <2>;
1138 num-pins = <128>;
1142 msi-parent = <&p0_its_dsa_a 0x40b20>;
1143 interrupt-controller;
1144 #interrupt-cells = <2>;
1145 num-pins = <3>;
1161 * when iommu-map entry is used along with the PCIe node.
1162 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
1165 compatible = "arm,smmu-v3";
1166 reg = <0x0 0xa0040000 0x0 0x20000>;
1167 #iommu-cells = <1>;
1168 dma-coherent;
1169 hisilicon,broken-prefetch-cmd;
1173 compatible = "arm,smmu-v3";
1174 reg = <0x0 0xd0040000 0x0 0x20000>;
1175 interrupt-parent = <&p0_mbigen_smmu_alg_a>;
1176 interrupts = <733 1>,
1177 <734 1>,
1178 <735 1>;
1179 interrupt-names = "eventq", "gerror", "priq";
1180 #iommu-cells = <1>;
1181 dma-coherent;
1182 hisilicon,broken-prefetch-cmd;
1185 compatible = "arm,smmu-v3";
1186 reg = <0x8 0xd0040000 0x0 0x20000>;
1187 interrupt-parent = <&p0_mbigen_smmu_alg_b>;
1188 interrupts = <733 1>,
1189 <734 1>,
1190 <735 1>;
1191 interrupt-names = "eventq", "gerror", "priq";
1192 #iommu-cells = <1>;
1193 dma-coherent;
1194 hisilicon,broken-prefetch-cmd;
1197 compatible = "arm,smmu-v3";
1198 reg = <0x400 0xd0040000 0x0 0x20000>;
1199 interrupt-parent = <&p1_mbigen_smmu_alg_a>;
1200 interrupts = <733 1>,
1201 <734 1>,
1202 <735 1>;
1203 interrupt-names = "eventq", "gerror", "priq";
1204 #iommu-cells = <1>;
1205 dma-coherent;
1206 hisilicon,broken-prefetch-cmd;
1209 compatible = "arm,smmu-v3";
1210 reg = <0x408 0xd0040000 0x0 0x20000>;
1211 interrupt-parent = <&p1_mbigen_smmu_alg_b>;
1212 interrupts = <733 1>,
1213 <734 1>,
1214 <735 1>;
1215 interrupt-names = "eventq", "gerror", "priq";
1216 #iommu-cells = <1>;
1217 dma-coherent;
1218 hisilicon,broken-prefetch-cmd;
1222 compatible = "simple-bus";
1223 #address-cells = <2>;
1224 #size-cells = <2>;
1228 compatible = "hisilicon,hip07-lpc";
1229 #size-cells = <1>;
1230 #address-cells = <2>;
1231 reg = <0x0 0xa01b0000 0x0 0x1000>;
1234 compatible = "ipmi-bt";
1236 reg = <0x01 0xe4 0x04>;
1242 compatible = "arm,sbsa-uart";
1243 reg = <0x0 0x602b0000 0x0 0x1000>;
1244 interrupt-parent = <&mbigen_uart>;
1246 current-speed = <115200>;
1247 reg-io-width = <4>;
1252 compatible = "generic-ohci";
1253 reg = <0x0 0xa7030000 0x0 0x10000>;
1254 interrupt-parent = <&mbigen_usb>;
1256 dma-coherent;
1261 compatible = "generic-ehci";
1262 reg = <0x0 0xa7020000 0x0 0x10000>;
1263 interrupt-parent = <&mbigen_usb>;
1265 dma-coherent;
1270 compatible = "hisilicon,peri-subctrl","syscon";
1271 reg = <0 0x60000000 0x0 0x10000>;
1275 compatible = "hisilicon,dsa-subctrl", "syscon";
1276 reg = <0x0 0xc0000000 0x0 0x10000>;
1281 reg = <0x0 0x78000010 0x0 0x100>;
1282 reg-io-width = <2>;
1286 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
1287 reg = <0x0 0xa0000000 0x0 0x10000>;
1292 reg = <0 0xc2200000 0x0 0x80000>;
1296 compatible = "hisilicon,hns-mdio";
1297 reg = <0x0 0x603c0000 0x0 0x1000>;
1298 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38
1299 0x531c 0x5a1c>;
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1303 phy0: ethernet-phy@0 {
1304 compatible = "ethernet-phy-ieee802.3-c22";
1305 reg = <0>;
1308 phy1: ethernet-phy@1 {
1309 compatible = "ethernet-phy-ieee802.3-c22";
1310 reg = <1>;
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1317 compatible = "hisilicon,hns-dsaf-v2";
1318 mode = "6port-16rss";
1319 reg = <0x0 0xc5000000 0x0 0x890000>,
1320 <0x0 0xc7000000 0x0 0x600000>;
1321 reg-names = "ppe-base", "dsaf-base";
1322 interrupt-parent = <&mbigen_dsaf0>;
1323 subctrl-syscon = <&dsa_subctrl>;
1324 reset-field-offset = <0>;
1326 <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
1327 <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
1328 <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
1329 <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
1330 <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
1331 <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
1332 <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
1333 <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
1334 <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
1335 <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
1336 <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
1337 <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
1338 <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
1339 <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
1340 <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
1341 <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
1342 <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
1343 <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
1344 <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
1345 <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
1346 <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
1347 <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
1348 <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
1349 <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
1350 <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
1351 <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
1352 <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
1353 <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
1354 <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
1355 <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
1356 <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
1357 <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
1358 <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
1359 <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
1360 <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
1361 <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
1362 <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
1363 <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
1364 <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
1365 <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
1366 <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
1367 <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
1368 <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
1369 <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
1370 <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
1371 <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
1372 <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
1373 <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
1374 <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
1375 <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
1376 <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
1377 <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
1378 <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
1379 <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
1380 <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
1381 <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
1382 <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
1383 <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
1384 <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
1385 <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
1386 <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
1387 <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
1388 <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
1389 <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
1390 <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
1391 <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
1392 <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
1393 <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
1394 <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
1395 <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
1396 <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
1397 <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
1398 <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
1399 <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
1400 <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
1401 <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
1402 <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
1403 <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
1404 <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
1405 <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
1406 <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
1407 <1340 1>, <1341 1>, <1342 1>, <1343 1>;
1409 desc-num = <0x400>;
1410 buf-size = <0x1000>;
1411 dma-coherent;
1413 port@0 {
1414 reg = <0>;
1415 serdes-syscon = <&serdes_ctrl>;
1416 cpld-syscon = <&dsa_cpld 0x0>;
1417 port-rst-offset = <0>;
1418 port-mode-offset = <0>;
1419 mc-mac-mask = [ff f0 00 00 00 00];
1420 media-type = "fiber";
1423 port@1 {
1424 reg = <1>;
1425 serdes-syscon = <&serdes_ctrl>;
1426 cpld-syscon = <&dsa_cpld 0x4>;
1427 port-rst-offset = <1>;
1428 port-mode-offset = <1>;
1429 mc-mac-mask = [ff f0 00 00 00 00];
1430 media-type = "fiber";
1435 phy-handle = <&phy0>;
1436 serdes-syscon = <&serdes_ctrl>;
1437 port-rst-offset = <4>;
1438 port-mode-offset = <2>;
1439 mc-mac-mask = [ff f0 00 00 00 00];
1440 media-type = "copper";
1445 phy-handle = <&phy1>;
1446 serdes-syscon = <&serdes_ctrl>;
1447 port-rst-offset = <5>;
1448 port-mode-offset = <3>;
1449 mc-mac-mask = [ff f0 00 00 00 00];
1450 media-type = "copper";
1455 compatible = "hisilicon,hns-nic-v2";
1456 ae-handle = <&dsaf0>;
1457 port-idx-in-ae = <4>;
1458 local-mac-address = [00 00 00 00 00 00];
1460 dma-coherent;
1464 compatible = "hisilicon,hns-nic-v2";
1465 ae-handle = <&dsaf0>;
1466 port-idx-in-ae = <5>;
1467 local-mac-address = [00 00 00 00 00 00];
1469 dma-coherent;
1472 eth2: ethernet@0{
1473 compatible = "hisilicon,hns-nic-v2";
1474 ae-handle = <&dsaf0>;
1475 port-idx-in-ae = <0>;
1476 local-mac-address = [00 00 00 00 00 00];
1478 dma-coherent;
1481 eth3: ethernet@1{
1482 compatible = "hisilicon,hns-nic-v2";
1483 ae-handle = <&dsaf0>;
1484 port-idx-in-ae = <1>;
1485 local-mac-address = [00 00 00 00 00 00];
1487 dma-coherent;
1491 compatible = "hisilicon,hns-roce-v1";
1492 reg = <0x0 0xc4000000 0x0 0x100000>;
1493 dma-coherent;
1494 eth-handle = <ð2 ð3 0 0 ð0 ð1>;
1495 dsaf-handle = <&dsaf0>;
1496 node-guid = [00 9A CD 00 00 01 02 03];
1497 #address-cells = <2>;
1498 #size-cells = <2>;
1499 interrupt-parent = <&mbigen_dsa_roce>;
1500 interrupts = <722 1>,
1501 <723 1>,
1502 <724 1>,
1503 <725 1>,
1504 <726 1>,
1505 <727 1>,
1506 <728 1>,
1507 <729 1>,
1508 <730 1>,
1509 <731 1>,
1510 <732 1>,
1511 <733 1>,
1512 <734 1>,
1513 <735 1>,
1514 <736 1>,
1515 <737 1>,
1516 <738 1>,
1517 <739 1>,
1518 <740 1>,
1519 <741 1>,
1520 <742 1>,
1521 <743 1>,
1522 <744 1>,
1523 <745 1>,
1524 <746 1>,
1525 <747 1>,
1526 <748 1>,
1527 <749 1>,
1528 <750 1>,
1529 <751 1>,
1530 <752 1>,
1531 <753 1>,
1532 <785 1>,
1535 interrupt-names = "hns-roce-comp-0",
1536 "hns-roce-comp-1",
1537 "hns-roce-comp-2",
1538 "hns-roce-comp-3",
1539 "hns-roce-comp-4",
1540 "hns-roce-comp-5",
1541 "hns-roce-comp-6",
1542 "hns-roce-comp-7",
1543 "hns-roce-comp-8",
1544 "hns-roce-comp-9",
1545 "hns-roce-comp-10",
1546 "hns-roce-comp-11",
1547 "hns-roce-comp-12",
1548 "hns-roce-comp-13",
1549 "hns-roce-comp-14",
1550 "hns-roce-comp-15",
1551 "hns-roce-comp-16",
1552 "hns-roce-comp-17",
1553 "hns-roce-comp-18",
1554 "hns-roce-comp-19",
1555 "hns-roce-comp-20",
1556 "hns-roce-comp-21",
1557 "hns-roce-comp-22",
1558 "hns-roce-comp-23",
1559 "hns-roce-comp-24",
1560 "hns-roce-comp-25",
1561 "hns-roce-comp-26",
1562 "hns-roce-comp-27",
1563 "hns-roce-comp-28",
1564 "hns-roce-comp-29",
1565 "hns-roce-comp-30",
1566 "hns-roce-comp-31",
1567 "hns-roce-async",
1568 "hns-roce-common";
1572 compatible = "hisilicon,hip07-sas-v2";
1573 reg = <0 0xc3000000 0 0x10000>;
1574 sas-addr = [50 01 88 20 16 00 00 00];
1575 hisilicon,sas-syscon = <&dsa_subctrl>;
1576 ctrl-reset-reg = <0xa60>;
1577 ctrl-reset-sts-reg = <0x5a30>;
1578 ctrl-clock-ena-reg = <0x338>;
1579 queue-count = <16>;
1580 phy-count = <8>;
1581 dma-coherent;
1582 interrupt-parent = <&mbigen_sas0>;
1602 <159 4>,<601 1>,<602 1>,<603 1>,<604 1>,
1603 <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
1604 <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
1605 <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
1606 <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
1607 <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
1608 <630 1>,<631 1>,<632 1>;
1613 compatible = "hisilicon,hip07-sas-v2";
1614 reg = <0 0xa2000000 0 0x10000>;
1615 sas-addr = [50 01 88 20 16 00 00 00];
1616 hisilicon,sas-syscon = <&pcie_subctl>;
1617 hip06-sas-v2-quirk-amt;
1618 ctrl-reset-reg = <0xa18>;
1619 ctrl-reset-sts-reg = <0x5a0c>;
1620 ctrl-clock-ena-reg = <0x318>;
1621 queue-count = <16>;
1622 phy-count = <8>;
1623 dma-coherent;
1624 interrupt-parent = <&mbigen_sas1>;
1644 <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
1645 <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
1646 <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
1647 <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
1648 <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
1649 <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
1650 <605 1>,<606 1>,<607 1>;
1655 compatible = "hisilicon,hip07-sas-v2";
1656 reg = <0 0xa3000000 0 0x10000>;
1657 sas-addr = [50 01 88 20 16 00 00 00];
1658 hisilicon,sas-syscon = <&pcie_subctl>;
1659 ctrl-reset-reg = <0xae0>;
1660 ctrl-reset-sts-reg = <0x5a70>;
1661 ctrl-clock-ena-reg = <0x3a8>;
1662 queue-count = <16>;
1663 phy-count = <9>;
1664 dma-coherent;
1665 interrupt-parent = <&mbigen_sas2>;
1685 <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
1686 <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
1687 <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
1688 <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
1689 <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
1690 <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
1691 <637 1>,<638 1>,<639 1>;
1696 compatible = "hisilicon,hip07-pcie-ecam";
1697 reg = <0 0xaf800000 0 0x800000>,
1698 <0 0xa00a0000 0 0x10000>;
1699 bus-range = <0xf8 0xff>;
1700 msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;
1701 msi-map-mask = <0xffff>;
1702 #address-cells = <3>;
1703 #size-cells = <2>;
1705 dma-coherent;
1706 ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000>,
1707 <0x01000000 0 0 0 0xaf7f0000 0 0x10000>;
1708 #interrupt-cells = <1>;
1709 interrupt-map-mask = <0xf800 0 0 7>;
1710 interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
1711 0x0 0 0 2 &mbigen_pcie2_a 671 4
1712 0x0 0 0 3 &mbigen_pcie2_a 671 4
1713 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
1717 compatible = "hisilicon,hip07-sec";
1718 reg = <0x0 0xd0000000 0x0 0x10000>,
1719 <0x0 0xd2000000 0x0 0x10000>,
1720 <0x0 0xd2010000 0x0 0x10000>,
1721 <0x0 0xd2020000 0x0 0x10000>,
1722 <0x0 0xd2030000 0x0 0x10000>,
1723 <0x0 0xd2040000 0x0 0x10000>,
1724 <0x0 0xd2050000 0x0 0x10000>,
1725 <0x0 0xd2060000 0x0 0x10000>,
1726 <0x0 0xd2070000 0x0 0x10000>,
1727 <0x0 0xd2080000 0x0 0x10000>,
1728 <0x0 0xd2090000 0x0 0x10000>,
1729 <0x0 0xd20a0000 0x0 0x10000>,
1730 <0x0 0xd20b0000 0x0 0x10000>,
1731 <0x0 0xd20c0000 0x0 0x10000>,
1732 <0x0 0xd20d0000 0x0 0x10000>,
1733 <0x0 0xd20e0000 0x0 0x10000>,
1734 <0x0 0xd20f0000 0x0 0x10000>,
1735 <0x0 0xd2100000 0x0 0x10000>;
1736 interrupt-parent = <&p0_mbigen_sec_a>;
1737 iommus = <&p0_smmu_alg_a 0x600>;
1738 dma-coherent;
1740 <577 1>, <578 4>,
1741 <579 1>, <580 4>,
1742 <581 1>, <582 4>,
1743 <583 1>, <584 4>,
1744 <585 1>, <586 4>,
1745 <587 1>, <588 4>,
1746 <589 1>, <590 4>,
1747 <591 1>, <592 4>,
1748 <593 1>, <594 4>,
1749 <595 1>, <596 4>,
1750 <597 1>, <598 4>,
1751 <599 1>, <600 4>,
1752 <601 1>, <602 4>,
1753 <603 1>, <604 4>,
1754 <605 1>, <606 4>,
1755 <607 1>, <608 4>;
1758 compatible = "hisilicon,hip07-sec";
1759 reg = <0x8 0xd0000000 0x0 0x10000>,
1760 <0x8 0xd2000000 0x0 0x10000>,
1761 <0x8 0xd2010000 0x0 0x10000>,
1762 <0x8 0xd2020000 0x0 0x10000>,
1763 <0x8 0xd2030000 0x0 0x10000>,
1764 <0x8 0xd2040000 0x0 0x10000>,
1765 <0x8 0xd2050000 0x0 0x10000>,
1766 <0x8 0xd2060000 0x0 0x10000>,
1767 <0x8 0xd2070000 0x0 0x10000>,
1768 <0x8 0xd2080000 0x0 0x10000>,
1769 <0x8 0xd2090000 0x0 0x10000>,
1770 <0x8 0xd20a0000 0x0 0x10000>,
1771 <0x8 0xd20b0000 0x0 0x10000>,
1772 <0x8 0xd20c0000 0x0 0x10000>,
1773 <0x8 0xd20d0000 0x0 0x10000>,
1774 <0x8 0xd20e0000 0x0 0x10000>,
1775 <0x8 0xd20f0000 0x0 0x10000>,
1776 <0x8 0xd2100000 0x0 0x10000>;
1777 interrupt-parent = <&p0_mbigen_sec_b>;
1778 iommus = <&p0_smmu_alg_b 0x600>;
1779 dma-coherent;
1781 <577 1>, <578 4>,
1782 <579 1>, <580 4>,
1783 <581 1>, <582 4>,
1784 <583 1>, <584 4>,
1785 <585 1>, <586 4>,
1786 <587 1>, <588 4>,
1787 <589 1>, <590 4>,
1788 <591 1>, <592 4>,
1789 <593 1>, <594 4>,
1790 <595 1>, <596 4>,
1791 <597 1>, <598 4>,
1792 <599 1>, <600 4>,
1793 <601 1>, <602 4>,
1794 <603 1>, <604 4>,
1795 <605 1>, <606 4>,
1796 <607 1>, <608 4>;
1799 compatible = "hisilicon,hip07-sec";
1800 reg = <0x400 0xd0000000 0x0 0x10000>,
1801 <0x400 0xd2000000 0x0 0x10000>,
1802 <0x400 0xd2010000 0x0 0x10000>,
1803 <0x400 0xd2020000 0x0 0x10000>,
1804 <0x400 0xd2030000 0x0 0x10000>,
1805 <0x400 0xd2040000 0x0 0x10000>,
1806 <0x400 0xd2050000 0x0 0x10000>,
1807 <0x400 0xd2060000 0x0 0x10000>,
1808 <0x400 0xd2070000 0x0 0x10000>,
1809 <0x400 0xd2080000 0x0 0x10000>,
1810 <0x400 0xd2090000 0x0 0x10000>,
1811 <0x400 0xd20a0000 0x0 0x10000>,
1812 <0x400 0xd20b0000 0x0 0x10000>,
1813 <0x400 0xd20c0000 0x0 0x10000>,
1814 <0x400 0xd20d0000 0x0 0x10000>,
1815 <0x400 0xd20e0000 0x0 0x10000>,
1816 <0x400 0xd20f0000 0x0 0x10000>,
1817 <0x400 0xd2100000 0x0 0x10000>;
1818 interrupt-parent = <&p1_mbigen_sec_a>;
1819 iommus = <&p1_smmu_alg_a 0x600>;
1820 dma-coherent;
1822 <577 1>, <578 4>,
1823 <579 1>, <580 4>,
1824 <581 1>, <582 4>,
1825 <583 1>, <584 4>,
1826 <585 1>, <586 4>,
1827 <587 1>, <588 4>,
1828 <589 1>, <590 4>,
1829 <591 1>, <592 4>,
1830 <593 1>, <594 4>,
1831 <595 1>, <596 4>,
1832 <597 1>, <598 4>,
1833 <599 1>, <600 4>,
1834 <601 1>, <602 4>,
1835 <603 1>, <604 4>,
1836 <605 1>, <606 4>,
1837 <607 1>, <608 4>;
1840 compatible = "hisilicon,hip07-sec";
1841 reg = <0x408 0xd0000000 0x0 0x10000>,
1842 <0x408 0xd2000000 0x0 0x10000>,
1843 <0x408 0xd2010000 0x0 0x10000>,
1844 <0x408 0xd2020000 0x0 0x10000>,
1845 <0x408 0xd2030000 0x0 0x10000>,
1846 <0x408 0xd2040000 0x0 0x10000>,
1847 <0x408 0xd2050000 0x0 0x10000>,
1848 <0x408 0xd2060000 0x0 0x10000>,
1849 <0x408 0xd2070000 0x0 0x10000>,
1850 <0x408 0xd2080000 0x0 0x10000>,
1851 <0x408 0xd2090000 0x0 0x10000>,
1852 <0x408 0xd20a0000 0x0 0x10000>,
1853 <0x408 0xd20b0000 0x0 0x10000>,
1854 <0x408 0xd20c0000 0x0 0x10000>,
1855 <0x408 0xd20d0000 0x0 0x10000>,
1856 <0x408 0xd20e0000 0x0 0x10000>,
1857 <0x408 0xd20f0000 0x0 0x10000>,
1858 <0x408 0xd2100000 0x0 0x10000>;
1859 interrupt-parent = <&p1_mbigen_sec_b>;
1860 iommus = <&p1_smmu_alg_b 0x600>;
1861 dma-coherent;
1863 <577 1>, <578 4>,
1864 <579 1>, <580 4>,
1865 <581 1>, <582 4>,
1866 <583 1>, <584 4>,
1867 <585 1>, <586 4>,
1868 <587 1>, <588 4>,
1869 <589 1>, <590 4>,
1870 <591 1>, <592 4>,
1871 <593 1>, <594 4>,
1872 <595 1>, <596 4>,
1873 <597 1>, <598 4>,
1874 <599 1>, <600 4>,
1875 <601 1>, <602 4>,
1876 <603 1>, <604 4>,
1877 <605 1>, <606 4>,
1878 <607 1>, <608 4>;