Lines Matching +full:0 +full:xa01b0000
23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
159 reg = <0x10201>;
167 reg = <0x10202>;
175 reg = <0x10203>;
183 reg = <0x10300>;
191 reg = <0x10301>;
199 reg = <0x10302>;
207 reg = <0x10303>;
237 redistributor-stride = <0x0 0x30000>;
238 reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
239 <0x0 0x4d100000 0 0x300000>, /* GICR */
240 <0x0 0xfe000000 0 0x10000>, /* GICC */
241 <0x0 0xfe010000 0 0x10000>, /* GICH */
242 <0x0 0xfe020000 0 0x10000>; /* GICV */
249 reg = <0x0 0xc6000000 0x0 0x40000>;
268 reg = <0x0 0xa0080000 0x0 0x10000>;
271 msi-parent = <&its_dsa 0x40080>;
278 msi-parent = <&its_dsa 0x40000>;
285 msi-parent = <&its_dsa 0x40040>;
292 msi-parent = <&its_dsa 0x40085>;
301 reg = <0x0 0xc0080000 0x0 0x10000>;
304 msi-parent = <&its_dsa 0x40800>;
311 msi-parent = <&its_dsa 0x40900>;
335 reg = <0x0 0xa0040000 0x0 0x20000>;
352 reg = <0x0 0xa01b0000 0x0 0x1000>;
357 reg = <0x01 0xe4 0x04>;
364 reg = <0x01 0x2f8 0x08>;
372 #clock-cells = <0>;
377 reg = <0x0 0xa7030000 0x0 0x10000>;
386 reg = <0x0 0xa7020000 0x0 0x10000>;
395 reg = <0 0x60000000 0x0 0x10000>;
400 reg = <0x0 0xc0000000 0x0 0x10000>;
405 reg = <0x0 0xa0000000 0x0 0x10000>;
410 reg = <0 0xc2200000 0x0 0x80000>;
415 reg = <0x0 0x603c0000 0x0 0x1000>;
416 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
418 #size-cells = <0>;
420 phy0: ethernet-phy@0 {
422 reg = <0>;
433 #size-cells = <0>;
436 reg = <0x0 0xc5000000 0x0 0x890000>,
437 <0x0 0xc7000000 0x0 0x600000>;
441 reset-field-offset = <0>;
526 desc-num = <0x400>;
527 buf-size = <0x1000>;
530 port@0 {
531 reg = <0>;
533 port-rst-offset = <0>;
534 port-mode-offset = <0>;
583 eth2: ethernet-0{
586 port-idx-in-ae = <0>;
603 reg = <0 0xc3000000 0 0x10000>;
606 ctrl-reset-reg = <0xa60>;
607 ctrl-reset-sts-reg = <0x5a30>;
608 ctrl-clock-ena-reg = <0x338>;
609 clocks = <&refclk 0>;
645 reg = <0 0xa2000000 0 0x10000>;
649 ctrl-reset-reg = <0xa18>;
650 ctrl-reset-sts-reg = <0x5a0c>;
651 ctrl-clock-ena-reg = <0x318>;
652 clocks = <&refclk 0>;
688 reg = <0 0xa3000000 0 0x10000>;
691 ctrl-reset-reg = <0xae0>;
692 ctrl-reset-sts-reg = <0x5a70>;
693 ctrl-clock-ena-reg = <0x3a8>;
694 clocks = <&refclk 0>;
730 reg = <0 0xb0000000 0 0x2000000>,
731 <0 0xa0090000 0 0x10000>;
732 bus-range = <0 31>;
733 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
734 msi-map-mask = <0xffff>;
739 ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000>,
740 <0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
742 interrupt-map-mask = <0xf800 0 0 7>;
743 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
744 0x0 0 0 2 &mbigen_pcie0 650 4
745 0x0 0 0 3 &mbigen_pcie0 650 4
746 0x0 0 0 4 &mbigen_pcie0 650 4>;