Lines Matching +full:0 +full:- +full:987
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
86 compatible = "arm,cortex-a57";
87 reg = <0x10000>;
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
95 reg = <0x10001>;
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
103 reg = <0x10002>;
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
111 reg = <0x10003>;
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
119 reg = <0x10100>;
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
127 reg = <0x10101>;
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
135 reg = <0x10102>;
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
143 reg = <0x10103>;
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
151 reg = <0x10200>;
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
159 reg = <0x10201>;
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
167 reg = <0x10202>;
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
175 reg = <0x10203>;
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
183 reg = <0x10300>;
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
191 reg = <0x10301>;
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
199 reg = <0x10302>;
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
207 reg = <0x10303>;
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
216 cluster1_l2: l2-cache1 {
220 cluster2_l2: l2-cache2 {
224 cluster3_l2: l2-cache3 {
229 gic: interrupt-controller@4d000000 {
230 compatible = "arm,gic-v3";
231 #interrupt-cells = <3>;
232 #address-cells = <2>;
233 #size-cells = <2>;
235 interrupt-controller;
236 #redistributor-regions = <1>;
237 redistributor-stride = <0x0 0x30000>;
238 reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
239 <0x0 0x4d100000 0 0x300000>, /* GICR */
240 <0x0 0xfe000000 0 0x10000>, /* GICC */
241 <0x0 0xfe010000 0 0x10000>, /* GICH */
242 <0x0 0xfe020000 0 0x10000>; /* GICV */
245 its_dsa: msi-controller@c6000000 {
246 compatible = "arm,gic-v3-its";
247 msi-controller;
248 #msi-cells = <1>;
249 reg = <0x0 0xc6000000 0x0 0x40000>;
254 compatible = "arm,armv8-timer";
262 compatible = "arm,cortex-a57-pmu";
267 compatible = "hisilicon,mbigen-v2";
268 reg = <0x0 0xa0080000 0x0 0x10000>;
271 msi-parent = <&its_dsa 0x40080>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 num-pins = <2>;
278 msi-parent = <&its_dsa 0x40000>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 num-pins = <128>;
285 msi-parent = <&its_dsa 0x40040>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 num-pins = <128>;
292 msi-parent = <&its_dsa 0x40085>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 num-pins = <10>;
300 compatible = "hisilicon,mbigen-v2";
301 reg = <0x0 0xc0080000 0x0 0x10000>;
304 msi-parent = <&its_dsa 0x40800>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 num-pins = <409>;
310 mbigen_sas0: intc-sas0 {
311 msi-parent = <&its_dsa 0x40900>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 num-pins = <128>;
330 * when iommu-map entry is used along with the PCIe node.
331 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
334 compatible = "arm,smmu-v3";
335 reg = <0x0 0xa0040000 0x0 0x20000>;
336 #iommu-cells = <1>;
337 dma-coherent;
338 hisilicon,broken-prefetch-cmd;
343 compatible = "simple-bus";
344 #address-cells = <2>;
345 #size-cells = <2>;
349 compatible = "hisilicon,hip06-lpc";
350 #size-cells = <1>;
351 #address-cells = <2>;
352 reg = <0x0 0xa01b0000 0x0 0x1000>;
355 compatible = "ipmi-bt";
357 reg = <0x01 0xe4 0x04>;
363 clock-frequency = <1843200>;
364 reg = <0x01 0x2f8 0x08>;
370 compatible = "fixed-clock";
371 clock-frequency = <50000000>;
372 #clock-cells = <0>;
376 compatible = "generic-ohci";
377 reg = <0x0 0xa7030000 0x0 0x10000>;
378 interrupt-parent = <&mbigen_usb>;
380 dma-coherent;
385 compatible = "generic-ehci";
386 reg = <0x0 0xa7020000 0x0 0x10000>;
387 interrupt-parent = <&mbigen_usb>;
389 dma-coherent;
394 compatible = "hisilicon,peri-subctrl","syscon";
395 reg = <0 0x60000000 0x0 0x10000>;
399 compatible = "hisilicon,dsa-subctrl", "syscon";
400 reg = <0x0 0xc0000000 0x0 0x10000>;
404 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
405 reg = <0x0 0xa0000000 0x0 0x10000>;
410 reg = <0 0xc2200000 0x0 0x80000>;
414 compatible = "hisilicon,hns-mdio";
415 reg = <0x0 0x603c0000 0x0 0x1000>;
416 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
417 #address-cells = <1>;
418 #size-cells = <0>;
420 phy0: ethernet-phy@0 {
421 compatible = "ethernet-phy-ieee802.3-c22";
422 reg = <0>;
425 phy1: ethernet-phy@1 {
426 compatible = "ethernet-phy-ieee802.3-c22";
432 #address-cells = <1>;
433 #size-cells = <0>;
434 compatible = "hisilicon,hns-dsaf-v2";
435 mode = "6port-16rss";
436 reg = <0x0 0xc5000000 0x0 0x890000>,
437 <0x0 0xc7000000 0x0 0x600000>;
438 reg-names = "ppe-base", "dsaf-base";
439 interrupt-parent = <&mbigen_dsaf0>;
440 subctrl-syscon = <&dsa_subctrl>;
441 reset-field-offset = <0>;
453 <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
526 desc-num = <0x400>;
527 buf-size = <0x1000>;
528 dma-coherent;
530 port@0 {
531 reg = <0>;
532 serdes-syscon = <&serdes_ctrl>;
533 port-rst-offset = <0>;
534 port-mode-offset = <0>;
535 media-type = "fiber";
540 serdes-syscon = <&serdes_ctrl>;
541 port-rst-offset = <1>;
542 port-mode-offset = <1>;
543 media-type = "fiber";
548 phy-handle = <&phy0>;
549 serdes-syscon = <&serdes_ctrl>;
550 port-rst-offset = <4>;
551 port-mode-offset = <2>;
552 media-type = "copper";
557 phy-handle = <&phy1>;
558 serdes-syscon = <&serdes_ctrl>;
559 port-rst-offset = <5>;
560 port-mode-offset = <3>;
561 media-type = "copper";
565 eth0: ethernet-4{
566 compatible = "hisilicon,hns-nic-v2";
567 ae-handle = <&dsaf0>;
568 port-idx-in-ae = <4>;
569 local-mac-address = [00 00 00 00 00 00];
571 dma-coherent;
574 eth1: ethernet-5{
575 compatible = "hisilicon,hns-nic-v2";
576 ae-handle = <&dsaf0>;
577 port-idx-in-ae = <5>;
578 local-mac-address = [00 00 00 00 00 00];
580 dma-coherent;
583 eth2: ethernet-0{
584 compatible = "hisilicon,hns-nic-v2";
585 ae-handle = <&dsaf0>;
586 port-idx-in-ae = <0>;
587 local-mac-address = [00 00 00 00 00 00];
589 dma-coherent;
592 eth3: ethernet-1{
593 compatible = "hisilicon,hns-nic-v2";
594 ae-handle = <&dsaf0>;
595 port-idx-in-ae = <1>;
596 local-mac-address = [00 00 00 00 00 00];
598 dma-coherent;
602 compatible = "hisilicon,hip06-sas-v2";
603 reg = <0 0xc3000000 0 0x10000>;
604 sas-addr = [50 01 88 20 16 00 00 00];
605 hisilicon,sas-syscon = <&dsa_subctrl>;
606 ctrl-reset-reg = <0xa60>;
607 ctrl-reset-sts-reg = <0x5a30>;
608 ctrl-clock-ena-reg = <0x338>;
609 clocks = <&refclk 0>;
610 queue-count = <16>;
611 phy-count = <8>;
612 dma-coherent;
613 interrupt-parent = <&mbigen_sas0>;
644 compatible = "hisilicon,hip06-sas-v2";
645 reg = <0 0xa2000000 0 0x10000>;
646 sas-addr = [50 01 88 20 16 00 00 00];
647 hisilicon,sas-syscon = <&pcie_subctl>;
648 hip06-sas-v2-quirk-amt;
649 ctrl-reset-reg = <0xa18>;
650 ctrl-reset-sts-reg = <0x5a0c>;
651 ctrl-clock-ena-reg = <0x318>;
652 clocks = <&refclk 0>;
653 queue-count = <16>;
654 phy-count = <8>;
655 dma-coherent;
656 interrupt-parent = <&mbigen_sas1>;
687 compatible = "hisilicon,hip06-sas-v2";
688 reg = <0 0xa3000000 0 0x10000>;
689 sas-addr = [50 01 88 20 16 00 00 00];
690 hisilicon,sas-syscon = <&pcie_subctl>;
691 ctrl-reset-reg = <0xae0>;
692 ctrl-reset-sts-reg = <0x5a70>;
693 ctrl-clock-ena-reg = <0x3a8>;
694 clocks = <&refclk 0>;
695 queue-count = <16>;
696 phy-count = <9>;
697 dma-coherent;
698 interrupt-parent = <&mbigen_sas2>;
729 compatible = "hisilicon,hip06-pcie-ecam";
730 reg = <0 0xb0000000 0 0x2000000>,
731 <0 0xa0090000 0 0x10000>;
732 bus-range = <0 31>;
733 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
734 msi-map-mask = <0xffff>;
735 #address-cells = <3>;
736 #size-cells = <2>;
738 dma-coherent;
739 ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000>,
740 <0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
741 #interrupt-cells = <1>;
742 interrupt-map-mask = <0xf800 0 0 7>;
743 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
744 0x0 0 0 2 &mbigen_pcie0 650 4
745 0x0 0 0 3 &mbigen_pcie0 650 4
746 0x0 0 0 4 &mbigen_pcie0 650 4>;