Lines Matching +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
86 compatible = "arm,cortex-a57";
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
216 cluster1_l2: l2-cache1 {
220 cluster2_l2: l2-cache2 {
224 cluster3_l2: l2-cache3 {
229 gic: interrupt-controller@4d000000 {
230 compatible = "arm,gic-v3";
231 #interrupt-cells = <3>;
232 #address-cells = <2>;
233 #size-cells = <2>;
235 interrupt-controller;
236 #redistributor-regions = <1>;
237 redistributor-stride = <0x0 0x30000>;
245 its_dsa: msi-controller@c6000000 {
246 compatible = "arm,gic-v3-its";
247 msi-controller;
248 #msi-cells = <1>;
254 compatible = "arm,armv8-timer";
262 compatible = "arm,cortex-a57-pmu";
267 compatible = "hisilicon,mbigen-v2";
271 msi-parent = <&its_dsa 0x40080>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 num-pins = <2>;
278 msi-parent = <&its_dsa 0x40000>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 num-pins = <128>;
285 msi-parent = <&its_dsa 0x40040>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 num-pins = <128>;
292 msi-parent = <&its_dsa 0x40085>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 num-pins = <10>;
300 compatible = "hisilicon,mbigen-v2";
304 msi-parent = <&its_dsa 0x40800>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 num-pins = <409>;
310 mbigen_sas0: intc-sas0 {
311 msi-parent = <&its_dsa 0x40900>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 num-pins = <128>;
330 * when iommu-map entry is used along with the PCIe node.
331 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
334 compatible = "arm,smmu-v3";
336 #iommu-cells = <1>;
337 dma-coherent;
338 hisilicon,broken-prefetch-cmd;
343 compatible = "simple-bus";
344 #address-cells = <2>;
345 #size-cells = <2>;
349 compatible = "hisilicon,hip06-lpc";
350 #size-cells = <1>;
351 #address-cells = <2>;
355 compatible = "ipmi-bt";
363 clock-frequency = <1843200>;
370 compatible = "fixed-clock";
371 clock-frequency = <50000000>;
372 #clock-cells = <0>;
376 compatible = "generic-ohci";
378 interrupt-parent = <&mbigen_usb>;
380 dma-coherent;
385 compatible = "generic-ehci";
387 interrupt-parent = <&mbigen_usb>;
389 dma-coherent;
394 compatible = "hisilicon,peri-subctrl","syscon";
399 compatible = "hisilicon,dsa-subctrl", "syscon";
404 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
414 compatible = "hisilicon,hns-mdio";
416 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
417 #address-cells = <1>;
418 #size-cells = <0>;
420 phy0: ethernet-phy@0 {
421 compatible = "ethernet-phy-ieee802.3-c22";
425 phy1: ethernet-phy@1 {
426 compatible = "ethernet-phy-ieee802.3-c22";
427 reg = <1>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 compatible = "hisilicon,hns-dsaf-v2";
435 mode = "6port-16rss";
438 reg-names = "ppe-base", "dsaf-base";
439 interrupt-parent = <&mbigen_dsaf0>;
440 subctrl-syscon = <&dsa_subctrl>;
441 reset-field-offset = <0>;
443 <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
444 <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
445 <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
446 <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
447 <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
448 <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
449 <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
450 <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
451 <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
452 <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
453 <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
454 <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
455 <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
456 <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
457 <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
458 <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
459 <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
460 <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
461 <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
462 <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
463 <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
464 <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
465 <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
466 <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
467 <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
468 <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
469 <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
470 <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
471 <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
472 <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
473 <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
474 <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
475 <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
476 <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
477 <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
478 <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
479 <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
480 <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
481 <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
482 <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
483 <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
484 <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
485 <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
486 <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
487 <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
488 <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
489 <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
490 <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
491 <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
492 <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
493 <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
494 <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
495 <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
496 <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
497 <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
498 <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
499 <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
500 <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
501 <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
502 <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
503 <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
504 <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
505 <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
506 <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
507 <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
508 <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
509 <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
510 <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
511 <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
512 <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
513 <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
514 <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
515 <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
516 <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
517 <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
518 <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
519 <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
520 <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
521 <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
522 <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
523 <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
524 <1340 1>, <1341 1>, <1342 1>, <1343 1>;
526 desc-num = <0x400>;
527 buf-size = <0x1000>;
528 dma-coherent;
532 serdes-syscon = <&serdes_ctrl>;
533 port-rst-offset = <0>;
534 port-mode-offset = <0>;
535 media-type = "fiber";
538 port@1 {
539 reg = <1>;
540 serdes-syscon = <&serdes_ctrl>;
541 port-rst-offset = <1>;
542 port-mode-offset = <1>;
543 media-type = "fiber";
548 phy-handle = <&phy0>;
549 serdes-syscon = <&serdes_ctrl>;
550 port-rst-offset = <4>;
551 port-mode-offset = <2>;
552 media-type = "copper";
557 phy-handle = <&phy1>;
558 serdes-syscon = <&serdes_ctrl>;
559 port-rst-offset = <5>;
560 port-mode-offset = <3>;
561 media-type = "copper";
565 eth0: ethernet-4{
566 compatible = "hisilicon,hns-nic-v2";
567 ae-handle = <&dsaf0>;
568 port-idx-in-ae = <4>;
569 local-mac-address = [00 00 00 00 00 00];
571 dma-coherent;
574 eth1: ethernet-5{
575 compatible = "hisilicon,hns-nic-v2";
576 ae-handle = <&dsaf0>;
577 port-idx-in-ae = <5>;
578 local-mac-address = [00 00 00 00 00 00];
580 dma-coherent;
583 eth2: ethernet-0{
584 compatible = "hisilicon,hns-nic-v2";
585 ae-handle = <&dsaf0>;
586 port-idx-in-ae = <0>;
587 local-mac-address = [00 00 00 00 00 00];
589 dma-coherent;
592 eth3: ethernet-1{
593 compatible = "hisilicon,hns-nic-v2";
594 ae-handle = <&dsaf0>;
595 port-idx-in-ae = <1>;
596 local-mac-address = [00 00 00 00 00 00];
598 dma-coherent;
602 compatible = "hisilicon,hip06-sas-v2";
604 sas-addr = [50 01 88 20 16 00 00 00];
605 hisilicon,sas-syscon = <&dsa_subctrl>;
606 ctrl-reset-reg = <0xa60>;
607 ctrl-reset-sts-reg = <0x5a30>;
608 ctrl-clock-ena-reg = <0x338>;
610 queue-count = <16>;
611 phy-count = <8>;
612 dma-coherent;
613 interrupt-parent = <&mbigen_sas0>;
633 <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
634 <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
635 <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
636 <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
637 <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
638 <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
639 <630 1>,<631 1>,<632 1>;
644 compatible = "hisilicon,hip06-sas-v2";
646 sas-addr = [50 01 88 20 16 00 00 00];
647 hisilicon,sas-syscon = <&pcie_subctl>;
648 hip06-sas-v2-quirk-amt;
649 ctrl-reset-reg = <0xa18>;
650 ctrl-reset-sts-reg = <0x5a0c>;
651 ctrl-clock-ena-reg = <0x318>;
653 queue-count = <16>;
654 phy-count = <8>;
655 dma-coherent;
656 interrupt-parent = <&mbigen_sas1>;
676 <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
677 <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
678 <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
679 <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
680 <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
681 <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
682 <605 1>,<606 1>,<607 1>;
687 compatible = "hisilicon,hip06-sas-v2";
689 sas-addr = [50 01 88 20 16 00 00 00];
690 hisilicon,sas-syscon = <&pcie_subctl>;
691 ctrl-reset-reg = <0xae0>;
692 ctrl-reset-sts-reg = <0x5a70>;
693 ctrl-clock-ena-reg = <0x3a8>;
695 queue-count = <16>;
696 phy-count = <9>;
697 dma-coherent;
698 interrupt-parent = <&mbigen_sas2>;
718 <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
719 <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
720 <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
721 <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
722 <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
723 <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
724 <637 1>,<638 1>,<639 1>;
729 compatible = "hisilicon,hip06-pcie-ecam";
732 bus-range = <0 31>;
733 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
734 msi-map-mask = <0xffff>;
735 #address-cells = <3>;
736 #size-cells = <2>;
738 dma-coherent;
741 #interrupt-cells = <1>;
742 interrupt-map-mask = <0xf800 0 0 7>;
743 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4