Lines Matching +full:interrupt +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <2>;
27 #size-cells = <0>;
29 cpu-map {
60 idle-states {
61 entry-method = "psci";
63 CPU_SLEEP: cpu-sleep {
64 compatible = "arm,idle-state";
65 local-timer-stop;
66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency-us = <700>;
68 exit-latency-us = <250>;
69 min-residency-us = <1000>;
72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = "arm,idle-state";
74 local-timer-stop;
75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency-us = <1000>;
77 exit-latency-us = <700>;
78 min-residency-us = <2700>;
79 wakeup-latency-us = <1500>;
84 compatible = "arm,cortex-a53";
87 enable-method = "psci";
88 next-level-cache = <&CLUSTER0_L2>;
90 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92 #cooling-cells = <2>; /* min followed by max */
93 dynamic-power-coefficient = <311>;
97 compatible = "arm,cortex-a53";
100 enable-method = "psci";
101 next-level-cache = <&CLUSTER0_L2>;
103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coefficient = <311>;
110 compatible = "arm,cortex-a53";
113 enable-method = "psci";
114 next-level-cache = <&CLUSTER0_L2>;
116 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <311>;
123 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 next-level-cache = <&CLUSTER0_L2>;
129 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; /* min followed by max */
132 dynamic-power-coefficient = <311>;
136 compatible = "arm,cortex-a53";
139 enable-method = "psci";
140 next-level-cache = <&CLUSTER1_L2>;
142 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; /* min followed by max */
145 dynamic-power-coefficient = <311>;
149 compatible = "arm,cortex-a53";
152 enable-method = "psci";
153 next-level-cache = <&CLUSTER1_L2>;
155 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coefficient = <311>;
162 compatible = "arm,cortex-a53";
165 enable-method = "psci";
166 next-level-cache = <&CLUSTER1_L2>;
168 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; /* min followed by max */
171 dynamic-power-coefficient = <311>;
175 compatible = "arm,cortex-a53";
178 enable-method = "psci";
179 next-level-cache = <&CLUSTER1_L2>;
181 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; /* min followed by max */
184 dynamic-power-coefficient = <311>;
187 CLUSTER0_L2: l2-cache0 {
191 CLUSTER1_L2: l2-cache1 {
196 cpu_opp_table: opp-table-0 {
197 compatible = "operating-points-v2";
198 opp-shared;
201 opp-hz = /bits/ 64 <208000000>;
202 opp-microvolt = <1040000>;
203 clock-latency-ns = <500000>;
206 opp-hz = /bits/ 64 <432000000>;
207 opp-microvolt = <1040000>;
208 clock-latency-ns = <500000>;
211 opp-hz = /bits/ 64 <729000000>;
212 opp-microvolt = <1090000>;
213 clock-latency-ns = <500000>;
216 opp-hz = /bits/ 64 <960000000>;
217 opp-microvolt = <1180000>;
218 clock-latency-ns = <500000>;
221 opp-hz = /bits/ 64 <1200000000>;
222 opp-microvolt = <1330000>;
223 clock-latency-ns = <500000>;
227 gic: interrupt-controller@f6801000 {
228 compatible = "arm,gic-400";
233 #address-cells = <0>;
234 #interrupt-cells = <3>;
235 interrupt-controller;
240 compatible = "arm,armv8-timer";
241 interrupt-parent = <&gic>;
249 compatible = "simple-bus";
250 #address-cells = <2>;
251 #size-cells = <2>;
255 compatible = "hisilicon,hi6220-sramctrl", "syscon";
260 compatible = "hisilicon,hi6220-aoctrl", "syscon";
262 #clock-cells = <1>;
263 #reset-cells = <1>;
267 compatible = "hisilicon,hi6220-sysctrl", "syscon";
269 #clock-cells = <1>;
270 #reset-cells = <1>;
274 compatible = "hisilicon,hi6220-mediactrl", "syscon";
276 #clock-cells = <1>;
277 #reset-cells = <1>;
281 compatible = "hisilicon,hi6220-pmctrl", "syscon";
283 #clock-cells = <1>;
287 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
289 #clock-cells = <1>;
298 compatible = "hisilicon,hi6220-stub-clk";
299 hisilicon,hi6220-clk-sram = <&sram>;
300 #clock-cells = <1>;
301 mbox-names = "mbox-tx";
311 clock-names = "uartclk", "apb_pclk";
320 clock-names = "uartclk", "apb_pclk";
321 pinctrl-names = "default";
322 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
324 dma-names = "rx", "tx";
334 clock-names = "uartclk", "apb_pclk";
335 pinctrl-names = "default";
336 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
346 clock-names = "uartclk", "apb_pclk";
347 pinctrl-names = "default";
348 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
358 clock-names = "uartclk", "apb_pclk";
359 pinctrl-names = "default";
360 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
365 compatible = "hisilicon,k3-dma-1.0";
367 #dma-cells = <1>;
368 dma-channels = <15>;
369 dma-requests = <32>;
372 dma-no-cci;
373 dma-type = "hi6220_dma";
385 clock-names = "timer1", "timer2", "apb_pclk";
393 clock-names = "apb_pclk";
401 clock-names = "apb_pclk";
405 compatible = "pinctrl-single";
407 #address-cells = <1>;
408 #size-cells = <1>;
409 #pinctrl-cells = <1>;
410 #gpio-range-cells = <3>;
411 pinctrl-single,register-width = <32>;
412 pinctrl-single,function-mask = <7>;
413 pinctrl-single,gpio-range = <
438 range: gpio-range {
439 #pinctrl-single,gpio-range-cells = <3>;
444 compatible = "pinconf-single";
446 #address-cells = <1>;
447 #size-cells = <1>;
448 #pinctrl-cells = <1>;
449 pinctrl-single,register-width = <32>;
453 compatible = "pinconf-single";
455 #address-cells = <1>;
456 #size-cells = <1>;
457 #pinctrl-cells = <1>;
458 pinctrl-single,register-width = <32>;
465 gpio-controller;
466 #gpio-cells = <2>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
470 clock-names = "apb_pclk";
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
482 clock-names = "apb_pclk";
489 gpio-controller;
490 #gpio-cells = <2>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
494 clock-names = "apb_pclk";
501 gpio-controller;
502 #gpio-cells = <2>;
503 gpio-ranges = <&pmx0 0 80 8>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
507 clock-names = "apb_pclk";
514 gpio-controller;
515 #gpio-cells = <2>;
516 gpio-ranges = <&pmx0 0 88 8>;
517 interrupt-controller;
518 #interrupt-cells = <2>;
520 clock-names = "apb_pclk";
527 gpio-controller;
528 #gpio-cells = <2>;
529 gpio-ranges = <&pmx0 0 96 8>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
533 clock-names = "apb_pclk";
540 gpio-controller;
541 #gpio-cells = <2>;
542 gpio-ranges = <&pmx0 0 104 8>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
546 clock-names = "apb_pclk";
553 gpio-controller;
554 #gpio-cells = <2>;
555 gpio-ranges = <&pmx0 0 112 8>;
556 interrupt-controller;
557 #interrupt-cells = <2>;
559 clock-names = "apb_pclk";
566 gpio-controller;
567 #gpio-cells = <2>;
568 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
572 clock-names = "apb_pclk";
579 gpio-controller;
580 #gpio-cells = <2>;
581 gpio-ranges = <&pmx0 0 8 8>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
585 clock-names = "apb_pclk";
592 gpio-controller;
593 #gpio-cells = <2>;
594 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
598 clock-names = "apb_pclk";
605 gpio-controller;
606 #gpio-cells = <2>;
607 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
608 interrupt-controller;
609 #interrupt-cells = <2>;
611 clock-names = "apb_pclk";
618 gpio-controller;
619 #gpio-cells = <2>;
620 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
621 interrupt-controller;
622 #interrupt-cells = <2>;
624 clock-names = "apb_pclk";
631 gpio-controller;
632 #gpio-cells = <2>;
633 gpio-ranges = <&pmx0 0 48 8>;
634 interrupt-controller;
635 #interrupt-cells = <2>;
637 clock-names = "apb_pclk";
644 gpio-controller;
645 #gpio-cells = <2>;
646 gpio-ranges = <&pmx0 0 56 8>;
647 interrupt-controller;
648 #interrupt-cells = <2>;
650 clock-names = "apb_pclk";
657 gpio-controller;
658 #gpio-cells = <2>;
659 gpio-ranges = <
664 interrupt-controller;
665 #interrupt-cells = <2>;
667 clock-names = "apb_pclk";
674 gpio-controller;
675 #gpio-cells = <2>;
676 gpio-ranges = <&pmx0 0 127 8>;
677 interrupt-controller;
678 #interrupt-cells = <2>;
680 clock-names = "apb_pclk";
687 gpio-controller;
688 #gpio-cells = <2>;
689 gpio-ranges = <&pmx0 0 135 8>;
690 interrupt-controller;
691 #interrupt-cells = <2>;
693 clock-names = "apb_pclk";
700 gpio-controller;
701 #gpio-cells = <2>;
702 gpio-ranges = <&pmx0 0 143 8>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
706 clock-names = "apb_pclk";
713 gpio-controller;
714 #gpio-cells = <2>;
715 gpio-ranges = <&pmx0 0 151 8>;
716 interrupt-controller;
717 #interrupt-cells = <2>;
719 clock-names = "apb_pclk";
726 bus-id = <0>;
727 enable-dma = <0>;
729 clock-names = "sspclk", "apb_pclk";
730 pinctrl-names = "default";
731 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
732 num-cs = <1>;
733 cs-gpios = <&gpio6 2 0>;
738 compatible = "snps,designware-i2c";
742 i2c-sda-hold-time-ns = <300>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
749 compatible = "snps,designware-i2c";
753 i2c-sda-hold-time-ns = <300>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
760 compatible = "snps,designware-i2c";
764 i2c-sda-hold-time-ns = <300>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
771 compatible = "hisilicon,hi6220-usb-phy";
772 #phy-cells = <0>;
773 phy-supply = <®_5v_hub>;
774 hisilicon,peripheral-syscon = <&sys_ctrl>;
778 compatible = "hisilicon,hi6220-usb";
781 phy-names = "usb2-phy";
783 clock-names = "otg";
785 g-rx-fifo-size = <512>;
786 g-np-tx-fifo-size = <128>;
787 g-tx-fifo-size = <128 128 128 128 128 128 128 128
793 compatible = "hisilicon,hi6220-mbox";
797 #mbox-cells = <3>;
801 compatible = "hisilicon,hi6220-dw-mshc";
805 clock-names = "ciu", "biu";
807 reset-names = "reset";
808 pinctrl-names = "default";
809 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
814 compatible = "hisilicon,hi6220-dw-mshc";
815 hisilicon,peripheral-syscon = <&ao_ctrl>;
818 #address-cells = <0x1>;
819 #size-cells = <0x0>;
821 clock-names = "ciu", "biu";
823 reset-names = "reset";
824 pinctrl-names = "default", "idle";
825 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
826 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
830 compatible = "hisilicon,hi6220-dw-mshc";
834 clock-names = "ciu", "biu";
836 reset-names = "reset";
837 pinctrl-names = "default", "idle";
838 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
839 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
848 clock-names = "wdog_clk", "apb_pclk";
856 clock-names = "thermal_clk";
857 #thermal-sensor-cells = <1>;
861 compatible = "hisilicon,hi6210-i2s";
863 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
866 clock-names = "dacodec", "i2s-base";
868 dma-names = "rx", "tx";
869 hisilicon,sysctrl-syscon = <&sys_ctrl>;
870 #sound-dai-cells = <1>;
873 thermal-zones {
875 cls0: cls0-thermal {
876 polling-delay = <1000>;
877 polling-delay-passive = <100>;
878 sustainable-power = <3326>;
881 thermal-sensors = <&tsensor 2>;
884 threshold: trip-point0 {
890 target: trip-point1 {
897 cooling-maps {
900 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
914 compatible = "hisilicon,hi6220-ade";
916 reg-names = "ade_base";
917 hisilicon,noc-syscon = <&medianoc_ade>;
919 interrupts = <0 115 4>; /* ldi interrupt */
925 clock-names = "clk_ade_core",
929 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
931 assigned-clock-rates = <360000000>, <288000000>;
932 dma-coherent;
937 remote-endpoint = <&dsi_in>;
943 compatible = "hisilicon,hi6220-dsi";
946 clock-names = "pclk";
950 #address-cells = <1>;
951 #size-cells = <0>;
957 remote-endpoint = <&ade_out>;
964 compatible = "arm,coresight-cpu-debug","arm,primecell";
967 clock-names = "apb_pclk";
972 compatible = "arm,coresight-cpu-debug","arm,primecell";
975 clock-names = "apb_pclk";
980 compatible = "arm,coresight-cpu-debug","arm,primecell";
983 clock-names = "apb_pclk";
988 compatible = "arm,coresight-cpu-debug","arm,primecell";
991 clock-names = "apb_pclk";
996 compatible = "arm,coresight-cpu-debug","arm,primecell";
999 clock-names = "apb_pclk";
1004 compatible = "arm,coresight-cpu-debug","arm,primecell";
1007 clock-names = "apb_pclk";
1012 compatible = "arm,coresight-cpu-debug","arm,primecell";
1015 clock-names = "apb_pclk";
1020 compatible = "arm,coresight-cpu-debug","arm,primecell";
1023 clock-names = "apb_pclk";
1028 compatible = "hisilicon,hi6220-mali", "arm,mali-450";
1030 interrupt-parent = <&gic>;
1043 interrupt-names = "gp",
1056 clock-names = "bus", "core";
1057 assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
1059 assigned-clock-rates = <500000000>, <144000000>;
1060 reset-names = "ao_g3d", "media_g3d";
1066 #include "hi6220-coresight.dtsi"