Lines Matching full:crg_ctrl
148 crg_ctrl: crg_ctrl@fff35000 { label
158 hisi,rst-syscon = <&crg_ctrl>;
167 pmuctrl: crg_ctrl@fff34000 {
207 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
208 <&crg_ctrl HI3670_PCLK>;
219 clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
220 <&crg_ctrl HI3670_PCLK>;
229 clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
230 <&crg_ctrl HI3670_PCLK>;
241 clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
242 <&crg_ctrl HI3670_PCLK>;
253 clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
254 <&crg_ctrl HI3670_PCLK>;
265 clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
266 <&crg_ctrl HI3670_PCLK>;
275 clocks = <&crg_ctrl HI3670_CLK_UART6>,
276 <&crg_ctrl HI3670_PCLK>;
292 clocks = <&crg_ctrl HI3670_PCLK_GPIO0>;
304 clocks = <&crg_ctrl HI3670_PCLK_GPIO1>;
317 clocks = <&crg_ctrl HI3670_PCLK_GPIO2>;
330 clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
343 clocks = <&crg_ctrl HI3670_PCLK_GPIO4>;
356 clocks = <&crg_ctrl HI3670_PCLK_GPIO5>;
369 clocks = <&crg_ctrl HI3670_PCLK_GPIO6>;
382 clocks = <&crg_ctrl HI3670_PCLK_GPIO7>;
395 clocks = <&crg_ctrl HI3670_PCLK_GPIO8>;
408 clocks = <&crg_ctrl HI3670_PCLK_GPIO9>;
421 clocks = <&crg_ctrl HI3670_PCLK_GPIO10>;
434 clocks = <&crg_ctrl HI3670_PCLK_GPIO11>;
447 clocks = <&crg_ctrl HI3670_PCLK_GPIO12>;
459 clocks = <&crg_ctrl HI3670_PCLK_GPIO13>;
471 clocks = <&crg_ctrl HI3670_PCLK_GPIO14>;
483 clocks = <&crg_ctrl HI3670_PCLK_GPIO15>;
496 clocks = <&crg_ctrl HI3670_PCLK_GPIO16>;
509 clocks = <&crg_ctrl HI3670_PCLK_GPIO17>;
548 clocks = <&crg_ctrl HI3670_PCLK_GPIO20>;
561 clocks = <&crg_ctrl HI3670_PCLK_GPIO21>;
671 clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
672 <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
689 clocks = <&crg_ctrl HI3670_CLK_GATE_SD>,
690 <&crg_ctrl HI3670_HCLK_GATE_SD>;
708 clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>,
709 <&crg_ctrl HI3670_HCLK_GATE_SDIO>;
768 clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>;
782 clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>;