Lines Matching +full:gpio +full:- +full:ranges
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
59 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
64 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
65 capacity-dmips-mhz = <592>;
67 operating-points-v2 = <&cluster0_opp>;
68 #cooling-cells = <2>;
69 dynamic-power-coefficient = <110>;
73 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 next-level-cache = <&A53_L2>;
78 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
79 capacity-dmips-mhz = <592>;
81 operating-points-v2 = <&cluster0_opp>;
82 #cooling-cells = <2>;
86 compatible = "arm,cortex-a53";
89 enable-method = "psci";
90 next-level-cache = <&A53_L2>;
91 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
92 capacity-dmips-mhz = <592>;
94 operating-points-v2 = <&cluster0_opp>;
95 #cooling-cells = <2>;
99 compatible = "arm,cortex-a53";
102 enable-method = "psci";
103 next-level-cache = <&A53_L2>;
104 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
105 capacity-dmips-mhz = <592>;
107 operating-points-v2 = <&cluster0_opp>;
108 #cooling-cells = <2>;
112 compatible = "arm,cortex-a73";
115 enable-method = "psci";
116 next-level-cache = <&A73_L2>;
117 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
118 capacity-dmips-mhz = <1024>;
120 operating-points-v2 = <&cluster1_opp>;
121 #cooling-cells = <2>;
122 dynamic-power-coefficient = <550>;
126 compatible = "arm,cortex-a73";
129 enable-method = "psci";
130 next-level-cache = <&A73_L2>;
131 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
132 capacity-dmips-mhz = <1024>;
134 operating-points-v2 = <&cluster1_opp>;
135 #cooling-cells = <2>;
139 compatible = "arm,cortex-a73";
142 enable-method = "psci";
143 next-level-cache = <&A73_L2>;
144 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
145 capacity-dmips-mhz = <1024>;
147 operating-points-v2 = <&cluster1_opp>;
148 #cooling-cells = <2>;
152 compatible = "arm,cortex-a73";
155 enable-method = "psci";
156 next-level-cache = <&A73_L2>;
157 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
158 capacity-dmips-mhz = <1024>;
160 operating-points-v2 = <&cluster1_opp>;
161 #cooling-cells = <2>;
164 idle-states {
165 entry-method = "psci";
167 CPU_SLEEP_0: cpu-sleep-0 {
168 compatible = "arm,idle-state";
169 local-timer-stop;
170 arm,psci-suspend-param = <0x0010000>;
171 entry-latency-us = <400>;
172 exit-latency-us = <650>;
173 min-residency-us = <1500>;
175 CLUSTER_SLEEP_0: cluster-sleep-0 {
176 compatible = "arm,idle-state";
177 local-timer-stop;
178 arm,psci-suspend-param = <0x1010000>;
179 entry-latency-us = <500>;
180 exit-latency-us = <1600>;
181 min-residency-us = <3500>;
185 CPU_SLEEP_1: cpu-sleep-1 {
186 compatible = "arm,idle-state";
187 local-timer-stop;
188 arm,psci-suspend-param = <0x0010000>;
189 entry-latency-us = <400>;
190 exit-latency-us = <550>;
191 min-residency-us = <1500>;
194 CLUSTER_SLEEP_1: cluster-sleep-1 {
195 compatible = "arm,idle-state";
196 local-timer-stop;
197 arm,psci-suspend-param = <0x1010000>;
198 entry-latency-us = <800>;
199 exit-latency-us = <2900>;
200 min-residency-us = <3500>;
204 A53_L2: l2-cache0 {
208 A73_L2: l2-cache1 {
213 cluster0_opp: opp-table-0 {
214 compatible = "operating-points-v2";
215 opp-shared;
218 opp-hz = /bits/ 64 <533000000>;
219 opp-microvolt = <700000>;
220 clock-latency-ns = <300000>;
224 opp-hz = /bits/ 64 <999000000>;
225 opp-microvolt = <800000>;
226 clock-latency-ns = <300000>;
230 opp-hz = /bits/ 64 <1402000000>;
231 opp-microvolt = <900000>;
232 clock-latency-ns = <300000>;
236 opp-hz = /bits/ 64 <1709000000>;
237 opp-microvolt = <1000000>;
238 clock-latency-ns = <300000>;
242 opp-hz = /bits/ 64 <1844000000>;
243 opp-microvolt = <1100000>;
244 clock-latency-ns = <300000>;
248 cluster1_opp: opp-table-1 {
249 compatible = "operating-points-v2";
250 opp-shared;
253 opp-hz = /bits/ 64 <903000000>;
254 opp-microvolt = <700000>;
255 clock-latency-ns = <300000>;
259 opp-hz = /bits/ 64 <1421000000>;
260 opp-microvolt = <800000>;
261 clock-latency-ns = <300000>;
265 opp-hz = /bits/ 64 <1805000000>;
266 opp-microvolt = <900000>;
267 clock-latency-ns = <300000>;
271 opp-hz = /bits/ 64 <2112000000>;
272 opp-microvolt = <1000000>;
273 clock-latency-ns = <300000>;
277 opp-hz = /bits/ 64 <2362000000>;
278 opp-microvolt = <1100000>;
279 clock-latency-ns = <300000>;
283 gic: interrupt-controller@e82b0000 {
284 compatible = "arm,gic-400";
289 #address-cells = <0>;
290 #interrupt-cells = <3>;
291 interrupt-controller;
296 a53-pmu {
297 compatible = "arm,cortex-a53-pmu";
302 interrupt-affinity = <&cpu0>,
308 a73-pmu {
309 compatible = "arm,cortex-a73-pmu";
314 interrupt-affinity = <&cpu4>,
321 compatible = "arm,armv8-timer";
322 interrupt-parent = <&gic>;
334 compatible = "simple-bus";
335 #address-cells = <2>;
336 #size-cells = <2>;
337 ranges;
340 compatible = "hisilicon,hi3660-crgctrl", "syscon";
342 #clock-cells = <1>;
346 compatible = "hisilicon,hi3660-reset";
347 #reset-cells = <2>;
348 hisi,rst-syscon = <&crg_ctrl>;
353 compatible = "hisilicon,hi3660-pctrl", "syscon";
355 #clock-cells = <1>;
359 compatible = "hisilicon,hi3660-pmuctrl", "syscon";
361 #clock-cells = <1>;
365 compatible = "hisilicon,hi3660-sctrl", "syscon";
367 #clock-cells = <1>;
371 compatible = "hisilicon,hi3660-iomcu", "syscon";
373 #clock-cells = <1>;
378 compatible = "hisilicon,hi3660-reset";
379 hisi,rst-syscon = <&iomcu>;
380 #reset-cells = <2>;
384 compatible = "hisilicon,hi3660-mbox";
388 #mbox-cells = <3>;
392 compatible = "hisilicon,hi3660-stub-clk";
394 #clock-cells = <1>;
406 clock-names = "timer1", "timer2", "apb_pclk";
410 compatible = "snps,designware-i2c";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clock-frequency = <400000>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
424 compatible = "snps,designware-i2c";
427 #address-cells = <1>;
428 #size-cells = <0>;
429 clock-frequency = <400000>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
438 compatible = "snps,designware-i2c";
441 #address-cells = <1>;
442 #size-cells = <0>;
443 clock-frequency = <400000>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
452 compatible = "snps,designware-i2c";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 clock-frequency = <400000>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
471 clock-names = "uartclk", "apb_pclk";
472 pinctrl-names = "default";
473 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
481 dma-names = "rx", "tx";
485 clock-names = "uartclk", "apb_pclk";
486 pinctrl-names = "default";
487 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
495 dma-names = "rx", "tx";
499 clock-names = "uartclk", "apb_pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
511 clock-names = "uartclk", "apb_pclk";
512 pinctrl-names = "default";
513 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
521 dma-names = "rx", "tx";
525 clock-names = "uartclk", "apb_pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
535 dma-names = "rx", "tx";
539 clock-names = "uartclk", "apb_pclk";
540 pinctrl-names = "default";
541 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
551 clock-names = "uartclk", "apb_pclk";
552 pinctrl-names = "default";
553 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
558 compatible = "hisilicon,k3-dma-1.0";
560 #dma-cells = <1>;
561 dma-channels = <16>;
562 dma-requests = <32>;
563 dma-channel-mask = <0xfffe>;
566 dma-no-cci;
567 dma-type = "hi3660_dma";
570 asp_dmac: dma-controller@e804b000 {
571 compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
573 #dma-cells = <1>;
574 dma-channels = <16>;
575 dma-requests = <32>;
577 interrupt-names = "asp_dma_irq";
585 clock-names = "apb_pclk";
588 gpio0: gpio@e8a0b000 {
592 gpio-controller;
593 #gpio-cells = <2>;
594 gpio-ranges = <&pmx0 1 0 7>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
598 clock-names = "apb_pclk";
601 gpio1: gpio@e8a0c000 {
605 gpio-controller;
606 #gpio-cells = <2>;
607 gpio-ranges = <&pmx0 1 7 7>;
608 interrupt-controller;
609 #interrupt-cells = <2>;
611 clock-names = "apb_pclk";
614 gpio2: gpio@e8a0d000 {
618 gpio-controller;
619 #gpio-cells = <2>;
620 gpio-ranges = <&pmx0 0 14 8>;
621 interrupt-controller;
622 #interrupt-cells = <2>;
624 clock-names = "apb_pclk";
627 gpio3: gpio@e8a0e000 {
631 gpio-controller;
632 #gpio-cells = <2>;
633 gpio-ranges = <&pmx0 0 22 8>;
634 interrupt-controller;
635 #interrupt-cells = <2>;
637 clock-names = "apb_pclk";
640 gpio4: gpio@e8a0f000 {
644 gpio-controller;
645 #gpio-cells = <2>;
646 gpio-ranges = <&pmx0 0 30 8>;
647 interrupt-controller;
648 #interrupt-cells = <2>;
650 clock-names = "apb_pclk";
653 gpio5: gpio@e8a10000 {
657 gpio-controller;
658 #gpio-cells = <2>;
659 gpio-ranges = <&pmx0 0 38 8>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
663 clock-names = "apb_pclk";
666 gpio6: gpio@e8a11000 {
670 gpio-controller;
671 #gpio-cells = <2>;
672 gpio-ranges = <&pmx0 0 46 8>;
673 interrupt-controller;
674 #interrupt-cells = <2>;
676 clock-names = "apb_pclk";
679 gpio7: gpio@e8a12000 {
683 gpio-controller;
684 #gpio-cells = <2>;
685 gpio-ranges = <&pmx0 0 54 8>;
686 interrupt-controller;
687 #interrupt-cells = <2>;
689 clock-names = "apb_pclk";
692 gpio8: gpio@e8a13000 {
696 gpio-controller;
697 #gpio-cells = <2>;
698 gpio-ranges = <&pmx0 0 62 8>;
699 interrupt-controller;
700 #interrupt-cells = <2>;
702 clock-names = "apb_pclk";
705 gpio9: gpio@e8a14000 {
709 gpio-controller;
710 #gpio-cells = <2>;
711 gpio-ranges = <&pmx0 0 70 8>;
712 interrupt-controller;
713 #interrupt-cells = <2>;
715 clock-names = "apb_pclk";
718 gpio10: gpio@e8a15000 {
722 gpio-controller;
723 #gpio-cells = <2>;
724 gpio-ranges = <&pmx0 0 78 8>;
725 interrupt-controller;
726 #interrupt-cells = <2>;
728 clock-names = "apb_pclk";
731 gpio11: gpio@e8a16000 {
735 gpio-controller;
736 #gpio-cells = <2>;
737 gpio-ranges = <&pmx0 0 86 8>;
738 interrupt-controller;
739 #interrupt-cells = <2>;
741 clock-names = "apb_pclk";
744 gpio12: gpio@e8a17000 {
748 gpio-controller;
749 #gpio-cells = <2>;
750 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
751 interrupt-controller;
752 #interrupt-cells = <2>;
754 clock-names = "apb_pclk";
757 gpio13: gpio@e8a18000 {
761 gpio-controller;
762 #gpio-cells = <2>;
763 gpio-ranges = <&pmx0 0 102 8>;
764 interrupt-controller;
765 #interrupt-cells = <2>;
767 clock-names = "apb_pclk";
770 gpio14: gpio@e8a19000 {
774 gpio-controller;
775 #gpio-cells = <2>;
776 gpio-ranges = <&pmx0 0 110 8>;
777 interrupt-controller;
778 #interrupt-cells = <2>;
780 clock-names = "apb_pclk";
783 gpio15: gpio@e8a1a000 {
787 gpio-controller;
788 #gpio-cells = <2>;
789 gpio-ranges = <&pmx0 0 118 6>;
790 interrupt-controller;
791 #interrupt-cells = <2>;
793 clock-names = "apb_pclk";
796 gpio16: gpio@e8a1b000 {
800 gpio-controller;
801 #gpio-cells = <2>;
802 interrupt-controller;
803 #interrupt-cells = <2>;
805 clock-names = "apb_pclk";
808 gpio17: gpio@e8a1c000 {
812 gpio-controller;
813 #gpio-cells = <2>;
814 interrupt-controller;
815 #interrupt-cells = <2>;
817 clock-names = "apb_pclk";
820 gpio18: gpio@ff3b4000 {
824 gpio-controller;
825 #gpio-cells = <2>;
826 gpio-ranges = <&pmx2 0 0 8>;
827 interrupt-controller;
828 #interrupt-cells = <2>;
830 clock-names = "apb_pclk";
833 gpio19: gpio@ff3b5000 {
837 gpio-controller;
838 #gpio-cells = <2>;
839 gpio-ranges = <&pmx2 0 8 4>;
840 interrupt-controller;
841 #interrupt-cells = <2>;
843 clock-names = "apb_pclk";
846 gpio20: gpio@e8a1f000 {
850 gpio-controller;
851 #gpio-cells = <2>;
852 gpio-ranges = <&pmx1 0 0 6>;
853 interrupt-controller;
854 #interrupt-cells = <2>;
856 clock-names = "apb_pclk";
859 gpio21: gpio@e8a20000 {
863 gpio-controller;
864 #gpio-cells = <2>;
865 interrupt-controller;
866 #interrupt-cells = <2>;
867 gpio-ranges = <&pmx3 0 0 6>;
869 clock-names = "apb_pclk";
872 gpio22: gpio@fff0b000 {
876 gpio-controller;
877 #gpio-cells = <2>;
879 gpio-ranges = <&pmx4 2 0 6>;
880 interrupt-controller;
881 #interrupt-cells = <2>;
883 clock-names = "apb_pclk";
886 gpio23: gpio@fff0c000 {
890 gpio-controller;
891 #gpio-cells = <2>;
893 gpio-ranges = <&pmx4 0 6 7>;
894 interrupt-controller;
895 #interrupt-cells = <2>;
897 clock-names = "apb_pclk";
900 gpio24: gpio@fff0d000 {
904 gpio-controller;
905 #gpio-cells = <2>;
907 gpio-ranges = <&pmx4 0 13 8>;
908 interrupt-controller;
909 #interrupt-cells = <2>;
911 clock-names = "apb_pclk";
914 gpio25: gpio@fff0e000 {
918 gpio-controller;
919 #gpio-cells = <2>;
921 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
922 interrupt-controller;
923 #interrupt-cells = <2>;
925 clock-names = "apb_pclk";
928 gpio26: gpio@fff0f000 {
932 gpio-controller;
933 #gpio-cells = <2>;
935 gpio-ranges = <&pmx4 0 28 8>;
936 interrupt-controller;
937 #interrupt-cells = <2>;
939 clock-names = "apb_pclk";
942 gpio27: gpio@fff10000 {
946 gpio-controller;
947 #gpio-cells = <2>;
949 gpio-ranges = <&pmx4 0 36 6>;
950 interrupt-controller;
951 #interrupt-cells = <2>;
953 clock-names = "apb_pclk";
956 gpio28: gpio@fff1d000 {
960 gpio-controller;
961 #gpio-cells = <2>;
962 interrupt-controller;
963 #interrupt-cells = <2>;
965 clock-names = "apb_pclk";
971 #address-cells = <1>;
972 #size-cells = <0>;
975 clock-names = "sspclk", "apb_pclk";
976 pinctrl-names = "default";
977 pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
978 num-cs = <1>;
979 cs-gpios = <&gpio27 2 0>;
986 #address-cells = <1>;
987 #size-cells = <0>;
990 clock-names = "sspclk", "apb_pclk";
991 pinctrl-names = "default";
992 pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
993 num-cs = <1>;
994 cs-gpios = <&gpio18 5 0>;
999 compatible = "hisilicon,kirin960-pcie";
1004 reg-names = "dbi", "apb", "phy", "config";
1005 bus-range = <0x0 0xff>;
1006 #address-cells = <3>;
1007 #size-cells = <2>;
1009 ranges = <0x02000000 0x0 0x00000000
1012 num-lanes = <1>;
1013 #interrupt-cells = <1>;
1015 interrupt-names = "msi";
1016 interrupt-map-mask = <0xf800 0 0 7>;
1017 interrupt-map = <0x0 0 0 1
1030 clock-names = "pcie_phy_ref", "pcie_aux",
1033 reset-gpios = <&gpio11 1 0 >;
1038 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
1043 interrupt-parent = <&gic>;
1047 clock-names = "ref_clk", "phy_clk";
1048 freq-table-hz = <0 0>,
1052 reset-names = "rst";
1057 compatible = "hisilicon,hi3660-dw-mshc";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1064 clock-names = "ciu", "biu";
1065 clock-frequency = <3200000>;
1067 reset-names = "reset";
1068 hisilicon,peripheral-syscon = <&sctrl>;
1069 card-detect-delay = <200>;
1075 compatible = "hisilicon,hi3660-dw-mshc";
1077 #address-cells = <0x1>;
1078 #size-cells = <0x0>;
1082 clock-names = "ciu", "biu";
1084 reset-names = "reset";
1085 card-detect-delay = <200>;
1095 clock-names = "wdog_clk", "apb_pclk";
1104 clock-names = "wdog_clk", "apb_pclk";
1108 compatible = "hisilicon,hi3660-tsensor";
1111 #thermal-sensor-cells = <1>;
1114 thermal-zones {
1116 cls0: cls0-thermal {
1117 polling-delay = <1000>;
1118 polling-delay-passive = <100>;
1119 sustainable-power = <4500>;
1122 thermal-sensors = <&tsensor 1>;
1125 threshold: trip-point0 {
1131 target: trip-point1 {
1138 cooling-maps {
1142 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1150 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1160 compatible = "syscon", "simple-mfd";
1163 usb_phy: usb-phy {
1164 compatible = "hisilicon,hi3660-usb-phy";
1165 #phy-cells = <0>;
1166 hisilicon,pericrg-syscon = <&crg_ctrl>;
1167 hisilicon,pctrl-syscon = <&pctrl>;
1168 hisilicon,eye-diagram-param = <0x22466e4>;
1178 clock-names = "ref", "bus_early";
1180 assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1181 assigned-clock-rates = <229000000>;
1190 phy-names = "usb3-phy";
1195 #include "hi3660-coresight.dtsi"