Lines Matching full:crg_ctrl

339 		crg_ctrl: crg_ctrl@fff35000 {  label
348 			hisi,rst-syscon = <&crg_ctrl>;
358 		pmuctrl: crg_ctrl@fff34000 {
403 			clocks = <&crg_ctrl HI3660_OSC32K>,
404 				 <&crg_ctrl HI3660_OSC32K>,
405 				 <&crg_ctrl HI3660_OSC32K>;
416 			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
430 			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
444 			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
458 			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
469 			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
470 				 <&crg_ctrl HI3660_PCLK>;
483 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
484 				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
497 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
498 				 <&crg_ctrl HI3660_PCLK>;
509 			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
510 				 <&crg_ctrl HI3660_PCLK>;
523 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
524 				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
537 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
538 				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
549 			clocks = <&crg_ctrl HI3660_CLK_UART6>,
550 				 <&crg_ctrl HI3660_PCLK>;
565 			clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
584 			clocks = <&crg_ctrl HI3660_PCLK>;
597 			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
610 			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
623 			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
636 			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
649 			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
662 			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
675 			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
688 			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
701 			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
714 			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
727 			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
740 			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
753 			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
766 			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
779 			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
792 			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
804 			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
816 			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
829 			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
842 			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
855 			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
868 			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
974 			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>;
989 			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>;
1025 			clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
1026 				 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
1027 				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
1028 				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
1029 				 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
1045 			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1046 				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1062 			clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
1063 				<&crg_ctrl HI3660_HCLK_GATE_SD>;
1080 			clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
1081 				 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
1093 			clocks = <&crg_ctrl HI3660_OSC32K>,
1094 				 <&crg_ctrl HI3660_OSC32K>;
1102 			clocks = <&crg_ctrl HI3660_OSC32K>,
1103 				 <&crg_ctrl HI3660_OSC32K>;
1166 				hisilicon,pericrg-syscon = <&crg_ctrl>;
1176 			clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
1177 				 <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1180 			assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;