Lines Matching +full:0 +full:x22466e4
25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
75 reg = <0x0 0x1>;
88 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
114 reg = <0x0 0x100>;
128 reg = <0x0 0x101>;
141 reg = <0x0 0x102>;
154 reg = <0x0 0x103>;
167 CPU_SLEEP_0: cpu-sleep-0 {
170 arm,psci-suspend-param = <0x0010000>;
175 CLUSTER_SLEEP_0: cluster-sleep-0 {
178 arm,psci-suspend-param = <0x1010000>;
188 arm,psci-suspend-param = <0x0010000>;
197 arm,psci-suspend-param = <0x1010000>;
213 cluster0_opp: opp-table-0 {
285 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
286 <0x0 0xe82b2000 0 0x2000>, /* GICC */
287 <0x0 0xe82b4000 0 0x2000>, /* GICH */
288 <0x0 0xe82b6000 0 0x2000>; /* GICV */
289 #address-cells = <0>;
341 reg = <0x0 0xfff35000 0x0 0x1000>;
354 reg = <0x0 0xe8a09000 0x0 0x2000>;
360 reg = <0x0 0xfff34000 0x0 0x1000>;
366 reg = <0x0 0xfff0a000 0x0 0x1000>;
372 reg = <0x0 0xffd7e000 0x0 0x1000>;
385 reg = <0x0 0xe896b000 0x0 0x1000>;
393 reg = <0x0 0xe896b500 0x0 0x0100>;
395 mboxes = <&mailbox 13 3 0>;
400 reg = <0x0 0xfff14000 0x0 0x1000>;
411 reg = <0x0 0xffd71000 0x0 0x1000>;
414 #size-cells = <0>;
417 resets = <&iomcu_rst 0x20 3>;
419 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
425 reg = <0x0 0xffd72000 0x0 0x1000>;
428 #size-cells = <0>;
431 resets = <&iomcu_rst 0x20 4>;
433 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
439 reg = <0x0 0xfdf0c000 0x0 0x1000>;
442 #size-cells = <0>;
445 resets = <&crg_rst 0x78 7>;
447 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
453 reg = <0x0 0xfdf0b000 0x0 0x1000>;
456 #size-cells = <0>;
459 resets = <&crg_rst 0x60 14>;
461 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
467 reg = <0x0 0xfdf02000 0x0 0x1000>;
473 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
479 reg = <0x0 0xfdf00000 0x0 0x1000>;
487 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
493 reg = <0x0 0xfdf03000 0x0 0x1000>;
501 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
507 reg = <0x0 0xffd74000 0x0 0x1000>;
513 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
519 reg = <0x0 0xfdf01000 0x0 0x1000>;
527 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
533 reg = <0x0 0xfdf05000 0x0 0x1000>;
541 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
547 reg = <0x0 0xfff32000 0x0 0x1000>;
553 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
559 reg = <0x0 0xfdf30000 0x0 0x1000>;
563 dma-channel-mask = <0xfffe>;
572 reg = <0x0 0xe804b000 0x0 0x1000>;
582 reg = <0x0 0Xfff04000 0x0 0x1000>;
590 reg = <0 0xe8a0b000 0 0x1000>;
594 gpio-ranges = <&pmx0 1 0 7>;
603 reg = <0 0xe8a0c000 0 0x1000>;
616 reg = <0 0xe8a0d000 0 0x1000>;
620 gpio-ranges = <&pmx0 0 14 8>;
629 reg = <0 0xe8a0e000 0 0x1000>;
633 gpio-ranges = <&pmx0 0 22 8>;
642 reg = <0 0xe8a0f000 0 0x1000>;
646 gpio-ranges = <&pmx0 0 30 8>;
655 reg = <0 0xe8a10000 0 0x1000>;
659 gpio-ranges = <&pmx0 0 38 8>;
668 reg = <0 0xe8a11000 0 0x1000>;
672 gpio-ranges = <&pmx0 0 46 8>;
681 reg = <0 0xe8a12000 0 0x1000>;
685 gpio-ranges = <&pmx0 0 54 8>;
694 reg = <0 0xe8a13000 0 0x1000>;
698 gpio-ranges = <&pmx0 0 62 8>;
707 reg = <0 0xe8a14000 0 0x1000>;
711 gpio-ranges = <&pmx0 0 70 8>;
720 reg = <0 0xe8a15000 0 0x1000>;
724 gpio-ranges = <&pmx0 0 78 8>;
733 reg = <0 0xe8a16000 0 0x1000>;
737 gpio-ranges = <&pmx0 0 86 8>;
746 reg = <0 0xe8a17000 0 0x1000>;
750 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
759 reg = <0 0xe8a18000 0 0x1000>;
763 gpio-ranges = <&pmx0 0 102 8>;
772 reg = <0 0xe8a19000 0 0x1000>;
776 gpio-ranges = <&pmx0 0 110 8>;
785 reg = <0 0xe8a1a000 0 0x1000>;
789 gpio-ranges = <&pmx0 0 118 6>;
798 reg = <0 0xe8a1b000 0 0x1000>;
810 reg = <0 0xe8a1c000 0 0x1000>;
822 reg = <0 0xff3b4000 0 0x1000>;
826 gpio-ranges = <&pmx2 0 0 8>;
835 reg = <0 0xff3b5000 0 0x1000>;
839 gpio-ranges = <&pmx2 0 8 4>;
848 reg = <0 0xe8a1f000 0 0x1000>;
852 gpio-ranges = <&pmx1 0 0 6>;
861 reg = <0 0xe8a20000 0 0x1000>;
867 gpio-ranges = <&pmx3 0 0 6>;
874 reg = <0 0xfff0b000 0 0x1000>;
879 gpio-ranges = <&pmx4 2 0 6>;
888 reg = <0 0xfff0c000 0 0x1000>;
893 gpio-ranges = <&pmx4 0 6 7>;
902 reg = <0 0xfff0d000 0 0x1000>;
907 gpio-ranges = <&pmx4 0 13 8>;
916 reg = <0 0xfff0e000 0 0x1000>;
921 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
930 reg = <0 0xfff0f000 0 0x1000>;
935 gpio-ranges = <&pmx4 0 28 8>;
944 reg = <0 0xfff10000 0 0x1000>;
949 gpio-ranges = <&pmx4 0 36 6>;
958 reg = <0 0xfff1d000 0 0x1000>;
970 reg = <0x0 0xffd68000 0x0 0x1000>;
972 #size-cells = <0>;
977 pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
979 cs-gpios = <&gpio27 2 0>;
985 reg = <0x0 0xff3b3000 0x0 0x1000>;
987 #size-cells = <0>;
992 pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
994 cs-gpios = <&gpio18 5 0>;
1000 reg = <0x0 0xf4000000 0x0 0x1000>,
1001 <0x0 0xff3fe000 0x0 0x1000>,
1002 <0x0 0xf3f20000 0x0 0x40000>,
1003 <0x0 0xf5000000 0x0 0x2000>;
1005 bus-range = <0x0 0xff>;
1009 ranges = <0x02000000 0x0 0x00000000
1010 0x0 0xf6000000
1011 0x0 0x02000000>;
1014 interrupts = <0 283 4>;
1016 interrupt-map-mask = <0xf800 0 0 7>;
1017 interrupt-map = <0x0 0 0 1
1019 <0x0 0 0 2
1021 <0x0 0 0 3
1023 <0x0 0 0 4
1033 reset-gpios = <&gpio11 1 0 >;
1039 /* 0: HCI standard */
1041 reg = <0x0 0xff3b0000 0x0 0x1000>,
1042 <0x0 0xff3b1000 0x0 0x1000>;
1048 freq-table-hz = <0 0>,
1049 <0 0>;
1050 /* offset: 0x84; bit: 12 */
1051 resets = <&crg_rst 0x84 12>;
1058 reg = <0x0 0xff37f000 0x0 0x1000>;
1060 #size-cells = <0>;
1066 resets = <&crg_rst 0x94 18>;
1076 reg = <0x0 0xff3ff000 0x0 0x1000>;
1077 #address-cells = <0x1>;
1078 #size-cells = <0x0>;
1083 resets = <&crg_rst 0x94 20>;
1091 reg = <0x0 0xe8a06000 0x0 0x1000>;
1100 reg = <0x0 0xe8a07000 0x0 0x1000>;
1109 reg = <0x0 0xfff30000 0x0 0x1000>;
1161 reg = <0x0 0xff200000 0x0 0x1000>;
1165 #phy-cells = <0>;
1168 hisilicon,eye-diagram-param = <0x22466e4>;
1174 reg = <0x0 0xff100000 0x0 0x100000>;
1183 resets = <&crg_rst 0x90 8>,
1184 <&crg_rst 0x90 7>,
1185 <&crg_rst 0x90 6>,
1186 <&crg_rst 0x90 5>;
1188 interrupts = <0 159 4>, <0 161 4>;