Lines Matching +full:psci +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2017-2021 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
25 enable-method = "psci";
26 next-level-cache = <&cluster0_l2>;
29 cpu1: cpu@1 {
31 compatible = "arm,cortex-a53";
33 enable-method = "psci";
34 next-level-cache = <&cluster0_l2>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 next-level-cache = <&cluster1_l2>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 next-level-cache = <&cluster1_l2>;
53 cluster0_l2: l2-cache0 {
57 cluster1_l2: l2-cache1 {
63 compatible = "arm,cortex-a53-pmu";
68 compatible = "arm,armv8-timer";
76 psci {
77 compatible = "arm,psci-1.0";
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
89 compatible = "nxp,s32g2-linflexuart",
90 "fsl,s32v234-linflexuart";
97 compatible = "nxp,s32g2-linflexuart",
98 "fsl,s32v234-linflexuart";
105 compatible = "nxp,s32g2-linflexuart",
106 "fsl,s32v234-linflexuart";
112 gic: interrupt-controller@50800000 {
113 compatible = "arm,gic-v3";
120 interrupt-controller;
121 #interrupt-cells = <3>;