Lines Matching +full:psci +full:- +full:0

1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6  * Copyright (c) 2017-2021 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 	interrupt-parent = <&gic>;
14 	#address-cells = <2>;
15 	#size-cells = <2>;
18 		#address-cells = <1>;
19 		#size-cells = <0>;
21 		cpu0: cpu@0 {
23 			compatible = "arm,cortex-a53";
24 			reg = <0x0>;
25 			enable-method = "psci";
26 			next-level-cache = <&cluster0_l2>;
31 			compatible = "arm,cortex-a53";
32 			reg = <0x1>;
33 			enable-method = "psci";
34 			next-level-cache = <&cluster0_l2>;
39 			compatible = "arm,cortex-a53";
40 			reg = <0x100>;
41 			enable-method = "psci";
42 			next-level-cache = <&cluster1_l2>;
47 			compatible = "arm,cortex-a53";
48 			reg = <0x101>;
49 			enable-method = "psci";
50 			next-level-cache = <&cluster1_l2>;
53 		cluster0_l2: l2-cache0 {
57 		cluster1_l2: l2-cache1 {
63 		compatible = "arm,cortex-a53-pmu";
68 		compatible = "arm,armv8-timer";
76 		psci {
77 			compatible = "arm,psci-1.0";
82 	soc@0 {
83 		compatible = "simple-bus";
84 		#address-cells = <1>;
85 		#size-cells = <1>;
86 		ranges = <0 0 0 0x80000000>;
89 			compatible = "nxp,s32g2-linflexuart",
90 				     "fsl,s32v234-linflexuart";
91 			reg = <0x401c8000 0x3000>;
97 			compatible = "nxp,s32g2-linflexuart",
98 				     "fsl,s32v234-linflexuart";
99 			reg = <0x401cc000 0x3000>;
105 			compatible = "nxp,s32g2-linflexuart",
106 				     "fsl,s32v234-linflexuart";
107 			reg = <0x402bc000 0x3000>;
112 		gic: interrupt-controller@50800000 {
113 			compatible = "arm,gic-v3";
114 			reg = <0x50800000 0x10000>,
115 			      <0x50880000 0x80000>,
116 			      <0x50400000 0x2000>,
117 			      <0x50410000 0x2000>,
118 			      <0x50420000 0x2000>;
120 			interrupt-controller;
121 			#interrupt-cells = <3>;