Lines Matching +full:imx7ulp +full:- +full:tpm
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
11 #include "imx8ulp-pinfunc.h"
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
33 #address-cells = <2>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a35";
40 enable-method = "psci";
41 next-level-cache = <&A35_L2>;
46 compatible = "arm,cortex-a35";
48 enable-method = "psci";
49 next-level-cache = <&A35_L2>;
52 A35_L2: l2-cache0 {
57 gic: interrupt-controller@2d400000 {
58 compatible = "arm,gic-v3";
61 #interrupt-cells = <3>;
62 interrupt-controller;
67 compatible = "arm,cortex-a35-pmu";
68 interrupt-parent = <&gic>;
71 interrupt-affinity = <&A35_0>, <&A35_1>;
75 compatible = "arm,psci-1.0";
80 compatible = "arm,armv8-timer";
82 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
87 frosc: clock-frosc {
88 compatible = "fixed-clock";
89 clock-frequency = <192000000>;
90 clock-output-names = "frosc";
91 #clock-cells = <0>;
94 lposc: clock-lposc {
95 compatible = "fixed-clock";
96 clock-frequency = <1000000>;
97 clock-output-names = "lposc";
98 #clock-cells = <0>;
101 rosc: clock-rosc {
102 compatible = "fixed-clock";
103 clock-frequency = <32768>;
104 clock-output-names = "rosc";
105 #clock-cells = <0>;
108 sosc: clock-sosc {
109 compatible = "fixed-clock";
110 clock-frequency = <24000000>;
111 clock-output-names = "sosc";
112 #clock-cells = <0>;
116 compatible = "mmio-sram";
119 #address-cells = <1>;
120 #size-cells = <1>;
123 scmi_buf: scmi-sram-section@0 {
124 compatible = "arm,scmi-shmem";
131 compatible = "arm,scmi-smc";
132 arm,smc-id = <0xc20000fe>;
133 #address-cells = <1>;
134 #size-cells = <0>;
139 #power-domain-cells = <1>;
144 #thermal-sensor-cells = <1>;
150 compatible = "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
156 compatible = "fsl,imx8ulp-mu-s4";
159 #mbox-cells = <2>;
163 compatible = "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
170 compatible = "fsl,imx8ulp-mu";
173 #mbox-cells = <2>;
178 compatible = "fsl,imx8ulp-mu";
182 #mbox-cells = <2>;
187 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
191 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
192 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
193 timeout-sec = <40>;
196 cgc1: clock-controller@292c0000 {
197 compatible = "fsl,imx8ulp-cgc1";
199 #clock-cells = <1>;
202 pcc3: clock-controller@292d0000 {
203 compatible = "fsl,imx8ulp-pcc3";
205 #clock-cells = <1>;
206 #reset-cells = <1>;
209 tpm5: tpm@29340000 {
210 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
215 clock-names = "ipg", "per";
220 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
225 clock-names = "per", "ipg";
226 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
227 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
228 assigned-clock-rates = <48000000>;
233 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
238 clock-names = "per", "ipg";
239 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
240 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
241 assigned-clock-rates = <48000000>;
246 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
250 clock-names = "ipg";
255 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
259 clock-names = "ipg";
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
271 clock-names = "per", "ipg";
272 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
273 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
274 assigned-clock-rates = <48000000>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
286 clock-names = "per", "ipg";
287 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
288 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
289 assigned-clock-rates = <48000000>;
295 compatible = "simple-bus";
297 #address-cells = <1>;
298 #size-cells = <1>;
301 pcc4: clock-controller@29800000 {
302 compatible = "fsl,imx8ulp-pcc4";
304 #clock-cells = <1>;
305 #reset-cells = <1>;
309 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
314 clock-names = "per", "ipg";
315 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
316 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
317 assigned-clock-rates = <48000000>;
322 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
327 clock-names = "per", "ipg";
328 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
329 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
330 assigned-clock-rates = <48000000>;
335 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
339 clock-names = "ipg";
344 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
348 clock-names = "ipg";
353 compatible = "fsl,imx8ulp-iomuxc1";
358 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
364 clock-names = "ipg", "ahb", "per";
365 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
366 fsl,tuning-start-tap = <20>;
367 fsl,tuning-step = <2>;
368 bus-width = <4>;
373 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
379 clock-names = "ipg", "ahb", "per";
380 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
381 fsl,tuning-start-tap = <20>;
382 fsl,tuning-step = <2>;
383 bus-width = <4>;
388 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
394 clock-names = "ipg", "ahb", "per";
395 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
396 fsl,tuning-start-tap = <20>;
397 fsl,tuning-step = <2>;
398 bus-width = <4>;
403 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
406 interrupt-names = "int0";
407 fsl,num-tx-queues = <1>;
408 fsl,num-rx-queues = <1>;
414 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
416 gpio-controller;
417 #gpio-cells = <2>;
419 interrupt-controller;
420 #interrupt-cells = <2>;
423 clock-names = "gpio", "port";
424 gpio-ranges = <&iomuxc1 0 32 24>;
428 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
430 gpio-controller;
431 #gpio-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
437 clock-names = "gpio", "port";
438 gpio-ranges = <&iomuxc1 0 64 32>;
442 compatible = "simple-bus";
444 #address-cells = <1>;
445 #size-cells = <1>;
448 cgc2: clock-controller@2da60000 {
449 compatible = "fsl,imx8ulp-cgc2";
451 #clock-cells = <1>;
454 pcc5: clock-controller@2da70000 {
455 compatible = "fsl,imx8ulp-pcc5";
457 #clock-cells = <1>;
458 #reset-cells = <1>;
463 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
465 gpio-controller;
466 #gpio-cells = <2>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
472 clock-names = "gpio", "port";
473 gpio-ranges = <&iomuxc1 0 0 24>;