Lines Matching +full:0 +full:x43
20 reg = <0x0 0x80000000 0 0x80000000>;
27 #clock-cells = <0>;
35 #clock-cells = <0>;
42 pinctrl-0 = <&pinctrl_lpuart5>;
49 pinctrl-0 = <&pinctrl_usdhc0>;
58 pinctrl-0 = <&pinctrl_enet>;
73 #size-cells = <0>;
85 MX8ULP_PAD_PTE15__ENET0_MDC 0x43
86 MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
87 MX8ULP_PAD_PTE17__ENET0_RXER 0x43
88 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
89 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
90 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
91 MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
92 MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
93 MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
94 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
95 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
101 MX8ULP_PAD_PTF14__LPUART5_TX 0x3
102 MX8ULP_PAD_PTF15__LPUART5_RX 0x3
108 MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
109 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
110 MX8ULP_PAD_PTD10__SDHC0_D0 0x43
111 MX8ULP_PAD_PTD9__SDHC0_D1 0x43
112 MX8ULP_PAD_PTD8__SDHC0_D2 0x43
113 MX8ULP_PAD_PTD7__SDHC0_D3 0x43
114 MX8ULP_PAD_PTD6__SDHC0_D4 0x43
115 MX8ULP_PAD_PTD5__SDHC0_D5 0x43
116 MX8ULP_PAD_PTD4__SDHC0_D6 0x43
117 MX8ULP_PAD_PTD3__SDHC0_D7 0x43
118 MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042