Lines Matching +full:opp +full:- +full:1200000000
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
55 #address-cells = <2>;
56 #size-cells = <0>;
58 /* We have 1 clusters with 4 Cortex-A35 cores */
61 compatible = "arm,cortex-a35";
63 enable-method = "psci";
64 i-cache-size = <0x8000>;
65 i-cache-line-size = <64>;
66 i-cache-sets = <256>;
67 d-cache-size = <0x8000>;
68 d-cache-line-size = <64>;
69 d-cache-sets = <128>;
70 next-level-cache = <&A35_L2>;
72 operating-points-v2 = <&a35_opp_table>;
73 #cooling-cells = <2>;
78 compatible = "arm,cortex-a35";
80 enable-method = "psci";
81 i-cache-size = <0x8000>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <256>;
84 d-cache-size = <0x8000>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&A35_L2>;
89 operating-points-v2 = <&a35_opp_table>;
90 #cooling-cells = <2>;
95 compatible = "arm,cortex-a35";
97 enable-method = "psci";
98 i-cache-size = <0x8000>;
99 i-cache-line-size = <64>;
100 i-cache-sets = <256>;
101 d-cache-size = <0x8000>;
102 d-cache-line-size = <64>;
103 d-cache-sets = <128>;
104 next-level-cache = <&A35_L2>;
106 operating-points-v2 = <&a35_opp_table>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a35";
114 enable-method = "psci";
115 i-cache-size = <0x8000>;
116 i-cache-line-size = <64>;
117 i-cache-sets = <256>;
118 d-cache-size = <0x8000>;
119 d-cache-line-size = <64>;
120 d-cache-sets = <128>;
121 next-level-cache = <&A35_L2>;
123 operating-points-v2 = <&a35_opp_table>;
124 #cooling-cells = <2>;
127 A35_L2: l2-cache0 {
129 cache-level = <2>;
130 cache-size = <0x80000>;
131 cache-line-size = <64>;
132 cache-sets = <1024>;
136 a35_opp_table: opp-table {
137 compatible = "operating-points-v2";
138 opp-shared;
140 opp-900000000 {
141 opp-hz = /bits/ 64 <900000000>;
142 opp-microvolt = <1000000>;
143 clock-latency-ns = <150000>;
146 opp-1200000000 {
147 opp-hz = /bits/ 64 <1200000000>;
148 opp-microvolt = <1100000>;
149 clock-latency-ns = <150000>;
150 opp-suspend;
154 gic: interrupt-controller@51a00000 {
155 compatible = "arm,gic-v3";
158 #interrupt-cells = <3>;
159 interrupt-controller;
163 reserved-memory {
164 #address-cells = <2>;
165 #size-cells = <2>;
168 decoder_boot: decoder-boot@84000000 {
170 no-map;
173 encoder_boot: encoder-boot@86000000 {
175 no-map;
178 decoder_rpc: decoder-rpc@92000000 {
180 no-map;
185 no-map;
188 encoder_rpc: encoder-rpc@94400000 {
190 no-map;
195 compatible = "arm,cortex-a35-pmu";
200 compatible = "arm,psci-1.0";
204 system-controller {
205 compatible = "fsl,imx-scu";
206 mbox-names = "tx0",
213 pd: power-controller {
214 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
215 #power-domain-cells = <1>;
218 clk: clock-controller {
219 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
220 #clock-cells = <2>;
224 compatible = "fsl,imx8qxp-iomuxc";
228 compatible = "fsl,imx8qxp-scu-ocotp";
229 #address-cells = <1>;
230 #size-cells = <1>;
234 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
240 compatible = "fsl,imx8qxp-sc-rtc";
244 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
245 timeout-sec = <60>;
248 tsens: thermal-sensor {
249 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
250 #thermal-sensor-cells = <1>;
255 compatible = "arm,armv8-timer";
257 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
262 xtal32k: clock-xtal32k {
263 compatible = "fixed-clock";
264 #clock-cells = <0>;
265 clock-frequency = <32768>;
266 clock-output-names = "xtal_32KHz";
269 xtal24m: clock-xtal24m {
270 compatible = "fixed-clock";
271 #clock-cells = <0>;
272 clock-frequency = <24000000>;
273 clock-output-names = "xtal_24MHz";
276 thermal_zones: thermal-zones {
277 cpu0-thermal {
278 polling-delay-passive = <250>;
279 polling-delay = <2000>;
280 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
296 cooling-maps {
299 cooling-device =
310 #include "imx8-ss-img.dtsi"
311 #include "imx8-ss-vpu.dtsi"
312 #include "imx8-ss-adma.dtsi"
313 #include "imx8-ss-conn.dtsi"
314 #include "imx8-ss-ddr.dtsi"
315 #include "imx8-ss-lsio.dtsi"
318 #include "imx8qxp-ss-img.dtsi"
319 #include "imx8qxp-ss-adma.dtsi"
320 #include "imx8qxp-ss-conn.dtsi"
321 #include "imx8qxp-ss-lsio.dtsi"