Lines Matching +full:imx8qxp +full:- +full:iomuxc
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
29 #address-cells = <2>;
30 #size-cells = <0>;
32 cpu-map {
60 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 i-cache-size = <0x8000>;
64 i-cache-line-size = <64>;
65 i-cache-sets = <256>;
66 d-cache-size = <0x8000>;
67 d-cache-line-size = <64>;
68 d-cache-sets = <128>;
69 next-level-cache = <&A53_L2>;
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
79 i-cache-sets = <256>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
82 d-cache-sets = <128>;
83 next-level-cache = <&A53_L2>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 i-cache-size = <0x8000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <128>;
97 next-level-cache = <&A53_L2>;
102 compatible = "arm,cortex-a53";
104 enable-method = "psci";
105 i-cache-size = <0x8000>;
106 i-cache-line-size = <64>;
107 i-cache-sets = <256>;
108 d-cache-size = <0x8000>;
109 d-cache-line-size = <64>;
110 d-cache-sets = <128>;
111 next-level-cache = <&A53_L2>;
116 compatible = "arm,cortex-a72";
118 enable-method = "psci";
119 i-cache-size = <0xC000>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <256>;
122 d-cache-size = <0x8000>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <256>;
125 next-level-cache = <&A72_L2>;
130 compatible = "arm,cortex-a72";
132 enable-method = "psci";
133 next-level-cache = <&A72_L2>;
136 A53_L2: l2-cache0 {
138 cache-level = <2>;
139 cache-size = <0x100000>;
140 cache-line-size = <64>;
141 cache-sets = <1024>;
144 A72_L2: l2-cache1 {
146 cache-level = <2>;
147 cache-size = <0x100000>;
148 cache-line-size = <64>;
149 cache-sets = <1024>;
153 gic: interrupt-controller@51a00000 {
154 compatible = "arm,gic-v3";
160 #interrupt-cells = <3>;
161 interrupt-controller;
163 interrupt-parent = <&gic>;
167 compatible = "arm,armv8-pmuv3";
172 compatible = "arm,psci-1.0";
177 compatible = "arm,armv8-timer";
179 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
184 system-controller {
185 compatible = "fsl,imx-scu";
186 mbox-names = "tx0",
193 pd: power-controller {
194 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
195 #power-domain-cells = <1>;
198 clk: clock-controller {
199 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
200 #clock-cells = <2>;
203 iomuxc: pinctrl { label
204 compatible = "fsl,imx8qm-iomuxc";
208 compatible = "fsl,imx8qxp-sc-rtc";
213 #include "imx8-ss-img.dtsi"
214 #include "imx8-ss-dma.dtsi"
215 #include "imx8-ss-conn.dtsi"
216 #include "imx8-ss-lsio.dtsi"
219 #include "imx8qm-ss-img.dtsi"
220 #include "imx8qm-ss-dma.dtsi"
221 #include "imx8qm-ss-conn.dtsi"
222 #include "imx8qm-ss-lsio.dtsi"