Lines Matching +full:imx8mq +full:- +full:pinfunc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
15 #include "imx8mq-pinfunc.h"
18 interrupt-parent = <&gpc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
45 ckil: clock-ckil {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
49 clock-output-names = "ckil";
52 osc_25m: clock-osc-25m {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 clock-output-names = "osc_25m";
59 osc_27m: clock-osc-27m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <27000000>;
63 clock-output-names = "osc_27m";
66 hdmi_phy_27m: clock-hdmi-phy-27m {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <27000000>;
70 clock-output-names = "hdmi_phy_27m";
73 clk_ext1: clock-ext1 {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <133000000>;
77 clock-output-names = "clk_ext1";
80 clk_ext2: clock-ext2 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <133000000>;
84 clock-output-names = "clk_ext2";
87 clk_ext3: clock-ext3 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <133000000>;
91 clock-output-names = "clk_ext3";
94 clk_ext4: clock-ext4 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <133000000>;
98 clock-output-names = "clk_ext4";
102 #address-cells = <1>;
103 #size-cells = <0>;
107 compatible = "arm,cortex-a53";
109 clock-latency = <61036>; /* two CLK32 periods */
111 enable-method = "psci";
112 i-cache-size = <0x8000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <128>;
118 next-level-cache = <&A53_L2>;
119 operating-points-v2 = <&a53_opp_table>;
120 #cooling-cells = <2>;
121 nvmem-cells = <&cpu_speed_grade>;
122 nvmem-cell-names = "speed_grade";
127 compatible = "arm,cortex-a53";
129 clock-latency = <61036>; /* two CLK32 periods */
131 enable-method = "psci";
132 i-cache-size = <0x8000>;
133 i-cache-line-size = <64>;
134 i-cache-sets = <256>;
135 d-cache-size = <0x8000>;
136 d-cache-line-size = <64>;
137 d-cache-sets = <128>;
138 next-level-cache = <&A53_L2>;
139 operating-points-v2 = <&a53_opp_table>;
140 #cooling-cells = <2>;
145 compatible = "arm,cortex-a53";
147 clock-latency = <61036>; /* two CLK32 periods */
149 enable-method = "psci";
150 i-cache-size = <0x8000>;
151 i-cache-line-size = <64>;
152 i-cache-sets = <256>;
153 d-cache-size = <0x8000>;
154 d-cache-line-size = <64>;
155 d-cache-sets = <128>;
156 next-level-cache = <&A53_L2>;
157 operating-points-v2 = <&a53_opp_table>;
158 #cooling-cells = <2>;
163 compatible = "arm,cortex-a53";
165 clock-latency = <61036>; /* two CLK32 periods */
167 enable-method = "psci";
168 i-cache-size = <0x8000>;
169 i-cache-line-size = <64>;
170 i-cache-sets = <256>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 next-level-cache = <&A53_L2>;
175 operating-points-v2 = <&a53_opp_table>;
176 #cooling-cells = <2>;
179 A53_L2: l2-cache0 {
181 cache-level = <2>;
182 cache-size = <0x100000>;
183 cache-line-size = <64>;
184 cache-sets = <1024>;
188 a53_opp_table: opp-table {
189 compatible = "operating-points-v2";
190 opp-shared;
192 opp-800000000 {
193 opp-hz = /bits/ 64 <800000000>;
194 opp-microvolt = <900000>;
196 opp-supported-hw = <0xf>, <0x4>;
197 clock-latency-ns = <150000>;
198 opp-suspend;
201 opp-1000000000 {
202 opp-hz = /bits/ 64 <1000000000>;
203 opp-microvolt = <900000>;
205 opp-supported-hw = <0xe>, <0x3>;
206 clock-latency-ns = <150000>;
207 opp-suspend;
210 opp-1300000000 {
211 opp-hz = /bits/ 64 <1300000000>;
212 opp-microvolt = <1000000>;
213 opp-supported-hw = <0xc>, <0x4>;
214 clock-latency-ns = <150000>;
215 opp-suspend;
218 opp-1500000000 {
219 opp-hz = /bits/ 64 <1500000000>;
220 opp-microvolt = <1000000>;
221 opp-supported-hw = <0x8>, <0x3>;
222 clock-latency-ns = <150000>;
223 opp-suspend;
228 compatible = "arm,cortex-a53-pmu";
230 interrupt-parent = <&gic>;
234 compatible = "arm,psci-1.0";
238 thermal-zones {
239 cpu_thermal: cpu-thermal {
240 polling-delay-passive = <250>;
241 polling-delay = <2000>;
242 thermal-sensors = <&tmu 0>;
245 cpu_alert: cpu-alert {
251 cpu-crit {
258 cooling-maps {
261 cooling-device =
270 gpu-thermal {
271 polling-delay-passive = <250>;
272 polling-delay = <2000>;
273 thermal-sensors = <&tmu 1>;
276 gpu_alert: gpu-alert {
282 gpu-crit {
289 cooling-maps {
292 cooling-device =
298 vpu-thermal {
299 polling-delay-passive = <250>;
300 polling-delay = <2000>;
301 thermal-sensors = <&tmu 2>;
304 vpu-crit {
314 compatible = "arm,armv8-timer";
316 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
319 interrupt-parent = <&gic>;
320 arm,no-tick-in-suspend;
324 compatible = "fsl,imx8mq-soc", "simple-bus";
325 #address-cells = <1>;
326 #size-cells = <1>;
328 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
329 nvmem-cells = <&imx8mq_uid>;
330 nvmem-cell-names = "soc_unique_id";
333 compatible = "fsl,aips-bus", "simple-bus";
335 #address-cells = <1>;
336 #size-cells = <1>;
340 #sound-dai-cells = <0>;
341 compatible = "fsl,imx8mq-sai";
347 clock-names = "bus", "mclk1", "mclk2", "mclk3";
349 dma-names = "rx", "tx";
354 #sound-dai-cells = <0>;
355 compatible = "fsl,imx8mq-sai";
361 clock-names = "bus", "mclk1", "mclk2", "mclk3";
363 dma-names = "rx", "tx";
368 #sound-dai-cells = <0>;
369 compatible = "fsl,imx8mq-sai";
375 clock-names = "bus", "mclk1", "mclk2", "mclk3";
377 dma-names = "rx", "tx";
382 #sound-dai-cells = <0>;
383 compatible = "fsl,imx8mq-sai";
389 clock-names = "bus", "mclk1", "mclk2", "mclk3";
391 dma-names = "rx", "tx";
396 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 gpio-ranges = <&iomuxc 0 10 30>;
409 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
414 gpio-controller;
415 #gpio-cells = <2>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 gpio-ranges = <&iomuxc 0 40 21>;
422 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
427 gpio-controller;
428 #gpio-cells = <2>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
431 gpio-ranges = <&iomuxc 0 61 26>;
435 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 gpio-ranges = <&iomuxc 0 87 32>;
448 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
453 gpio-controller;
454 #gpio-cells = <2>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 gpio-ranges = <&iomuxc 0 119 30>;
461 compatible = "fsl,imx8mq-tmu";
465 little-endian;
466 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
467 fsl,tmu-calibration = <0x00000000 0x00000023>,
510 #thermal-sensor-cells = <1>;
514 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
522 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
530 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
537 sdma2: dma-controller@302c0000 {
538 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
543 clock-names = "ipg", "ahb";
544 #dma-cells = <3>;
545 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
548 lcdif: lcd-controller@30320000 {
549 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
553 clock-names = "pix";
554 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
558 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
561 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
566 remote-endpoint = <&mipi_dsi_lcdif_in>;
572 compatible = "fsl,imx8mq-iomuxc";
577 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
578 "syscon", "simple-mfd";
581 mux: mux-controller {
582 compatible = "mmio-mux";
583 #mux-control-cells = <1>;
584 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
589 compatible = "fsl,imx8mq-ocotp", "syscon";
592 #address-cells = <1>;
593 #size-cells = <1>;
595 imx8mq_uid: soc-uid@410 {
599 cpu_speed_grade: speed-grade@10 {
603 fec_mac_address: mac-address@90 {
609 compatible = "fsl,imx8mq-anatop", "syscon";
615 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
618 snvs_rtc: snvs-rtc-lp{
619 compatible = "fsl,sec-v4.0-mon-rtc-lp";
625 clock-names = "snvs-rtc";
628 snvs_pwrkey: snvs-powerkey {
629 compatible = "fsl,sec-v4.0-pwrkey";
633 clock-names = "snvs-pwrkey";
635 wakeup-source;
640 clk: clock-controller@30380000 {
641 compatible = "fsl,imx8mq-ccm";
645 #clock-cells = <1>;
649 clock-names = "ckil", "osc_25m", "osc_27m",
652 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
660 assigned-clock-rates = <0>, <0>,
667 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
675 src: reset-controller@30390000 {
676 compatible = "fsl,imx8mq-src", "syscon";
679 #reset-cells = <1>;
683 compatible = "fsl,imx8mq-gpc";
686 interrupt-parent = <&gic>;
687 interrupt-controller;
688 #interrupt-cells = <3>;
691 #address-cells = <1>;
692 #size-cells = <0>;
694 pgc_mipi: power-domain@0 {
695 #power-domain-cells = <0>;
714 pgc_pcie: power-domain@1 {
715 #power-domain-cells = <0>;
717 power-domains = <&pgc_pcie2>;
720 pgc_otg1: power-domain@2 {
721 #power-domain-cells = <0>;
725 pgc_otg2: power-domain@3 {
726 #power-domain-cells = <0>;
730 pgc_ddr1: power-domain@4 {
731 #power-domain-cells = <0>;
735 pgc_gpu: power-domain@5 {
736 #power-domain-cells = <0>;
744 pgc_vpu: power-domain@6 {
745 #power-domain-cells = <0>;
750 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
754 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
758 assigned-clock-rates = <600000000>,
764 pgc_disp: power-domain@7 {
765 #power-domain-cells = <0>;
769 pgc_mipi_csi1: power-domain@8 {
770 #power-domain-cells = <0>;
774 pgc_mipi_csi2: power-domain@9 {
775 #power-domain-cells = <0>;
779 pgc_pcie2: power-domain@a {
780 #power-domain-cells = <0>;
788 compatible = "fsl,aips-bus", "simple-bus";
790 #address-cells = <1>;
791 #size-cells = <1>;
795 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
800 clock-names = "ipg", "per";
801 #pwm-cells = <3>;
806 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
811 clock-names = "ipg", "per";
812 #pwm-cells = <3>;
817 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
822 clock-names = "ipg", "per";
823 #pwm-cells = <3>;
828 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
833 clock-names = "ipg", "per";
834 #pwm-cells = <3>;
839 compatible = "nxp,sysctr-timer";
843 clock-names = "per";
848 compatible = "fsl,aips-bus", "simple-bus";
850 #address-cells = <1>;
851 #size-cells = <1>;
856 compatible = "fsl,imx35-spdif";
869 clock-names = "core", "rxtx0",
875 dma-names = "rx", "tx";
880 #address-cells = <1>;
881 #size-cells = <0>;
882 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
887 clock-names = "ipg", "per";
889 dma-names = "rx", "tx";
894 #address-cells = <1>;
895 #size-cells = <0>;
896 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
901 clock-names = "ipg", "per";
903 dma-names = "rx", "tx";
908 #address-cells = <1>;
909 #size-cells = <0>;
910 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
915 clock-names = "ipg", "per";
917 dma-names = "rx", "tx";
922 compatible = "fsl,imx8mq-uart",
923 "fsl,imx6q-uart";
928 clock-names = "ipg", "per";
933 compatible = "fsl,imx8mq-uart",
934 "fsl,imx6q-uart";
939 clock-names = "ipg", "per";
944 compatible = "fsl,imx8mq-uart",
945 "fsl,imx6q-uart";
950 clock-names = "ipg", "per";
955 compatible = "fsl,imx35-spdif";
968 clock-names = "core", "rxtx0",
974 dma-names = "rx", "tx";
979 #sound-dai-cells = <0>;
980 compatible = "fsl,imx8mq-sai";
986 clock-names = "bus", "mclk1", "mclk2", "mclk3";
988 dma-names = "rx", "tx";
993 #sound-dai-cells = <0>;
994 compatible = "fsl,imx8mq-sai";
1000 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1002 dma-names = "rx", "tx";
1007 compatible = "fsl,sec-v4.0";
1008 #address-cells = <1>;
1009 #size-cells = <1>;
1015 clock-names = "aclk", "ipg";
1018 compatible = "fsl,sec-v4.0-job-ring";
1025 compatible = "fsl,sec-v4.0-job-ring";
1031 compatible = "fsl,sec-v4.0-job-ring";
1037 mipi_dsi: mipi-dsi@30a00000 {
1038 compatible = "fsl,imx8mq-nwl-dsi";
1045 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
1046 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1049 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1051 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1053 mux-controls = <&mux 0>;
1054 power-domains = <&pgc_mipi>;
1056 phy-names = "dphy";
1061 reset-names = "byte", "dpi", "esc", "pclk";
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1074 remote-endpoint = <&lcdif_mipi_dsi>;
1081 compatible = "fsl,imx8mq-mipi-dphy";
1084 clock-names = "phy_ref";
1085 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1089 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1092 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1093 #phy-cells = <0>;
1094 power-domains = <&pgc_mipi>;
1099 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1109 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1119 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1129 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1139 compatible = "fsl,imx8mq-uart",
1140 "fsl,imx6q-uart";
1145 clock-names = "ipg", "per";
1150 compatible = "fsl,imx8mq-mipi-csi2";
1155 clock-names = "core", "esc", "ui";
1156 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1159 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1160 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1163 power-domains = <&pgc_mipi_csi1>;
1167 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1169 interconnect-names = "dram";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1180 remote-endpoint = <&csi1_ep>;
1187 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1191 clock-names = "mclk";
1196 remote-endpoint = <&csi1_mipi_ep>;
1202 compatible = "fsl,imx8mq-mipi-csi2";
1207 clock-names = "core", "esc", "ui";
1208 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1211 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1212 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1215 power-domains = <&pgc_mipi_csi2>;
1219 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1221 interconnect-names = "dram";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1232 remote-endpoint = <&csi2_ep>;
1239 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1243 clock-names = "mclk";
1248 remote-endpoint = <&csi2_mipi_ep>;
1254 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1258 #mbox-cells = <2>;
1262 compatible = "fsl,imx8mq-usdhc",
1263 "fsl,imx7d-usdhc";
1269 clock-names = "ipg", "ahb", "per";
1270 fsl,tuning-start-tap = <20>;
1271 fsl,tuning-step = <2>;
1272 bus-width = <4>;
1277 compatible = "fsl,imx8mq-usdhc",
1278 "fsl,imx7d-usdhc";
1284 clock-names = "ipg", "ahb", "per";
1285 fsl,tuning-start-tap = <20>;
1286 fsl,tuning-step = <2>;
1287 bus-width = <4>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1294 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1297 reg-names = "QuadSPI", "QuadSPI-memory";
1301 clock-names = "qspi_en", "qspi";
1305 sdma1: dma-controller@30bd0000 {
1306 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1311 clock-names = "ipg", "ahb";
1312 #dma-cells = <3>;
1313 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1317 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1328 clock-names = "ipg", "ahb", "ptp",
1330 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1334 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1338 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1339 fsl,num-tx-queues = <3>;
1340 fsl,num-rx-queues = <3>;
1341 nvmem-cells = <&fec_mac_address>;
1342 nvmem-cell-names = "mac-address";
1343 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1349 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1353 #interconnect-cells = <1>;
1354 operating-points-v2 = <&noc_opp_table>;
1356 noc_opp_table: opp-table {
1357 compatible = "operating-points-v2";
1359 opp-133M {
1360 opp-hz = /bits/ 64 <133333333>;
1363 opp-400M {
1364 opp-hz = /bits/ 64 <400000000>;
1367 opp-800M {
1368 opp-hz = /bits/ 64 <800000000>;
1374 compatible = "fsl,aips-bus", "simple-bus";
1376 #address-cells = <1>;
1377 #size-cells = <1>;
1380 irqsteer: interrupt-controller@32e2d000 {
1381 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1385 clock-names = "ipg";
1387 fsl,num-irqs = <64>;
1388 interrupt-controller;
1389 #interrupt-cells = <1>;
1401 clock-names = "core", "shader", "bus", "reg";
1402 #cooling-cells = <2>;
1403 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1408 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1413 assigned-clock-rates = <800000000>, <800000000>,
1415 power-domains = <&pgc_gpu>;
1419 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1424 clock-names = "bus_early", "ref", "suspend";
1425 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1427 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1429 assigned-clock-rates = <500000000>, <100000000>;
1432 phy-names = "usb2-phy", "usb3-phy";
1433 power-domains = <&pgc_otg1>;
1434 usb3-resume-missing-cas;
1438 usb3_phy0: usb-phy@381f0040 {
1439 compatible = "fsl,imx8mq-usb-phy";
1442 clock-names = "phy";
1443 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1444 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1445 assigned-clock-rates = <100000000>;
1446 #phy-cells = <0>;
1451 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1456 clock-names = "bus_early", "ref", "suspend";
1457 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1459 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1461 assigned-clock-rates = <500000000>, <100000000>;
1464 phy-names = "usb2-phy", "usb3-phy";
1465 power-domains = <&pgc_otg2>;
1466 usb3-resume-missing-cas;
1470 usb3_phy1: usb-phy@382f0040 {
1471 compatible = "fsl,imx8mq-usb-phy";
1474 clock-names = "phy";
1475 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1476 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1477 assigned-clock-rates = <100000000>;
1478 #phy-cells = <0>;
1482 vpu_g1: video-codec@38300000 {
1483 compatible = "nxp,imx8mq-vpu-g1";
1487 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
1490 vpu_g2: video-codec@38310000 {
1491 compatible = "nxp,imx8mq-vpu-g2";
1495 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
1498 vpu_blk_ctrl: blk-ctrl@38320000 {
1499 compatible = "fsl,imx8mq-vpu-blk-ctrl";
1501 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
1502 power-domain-names = "bus", "g1", "g2";
1505 clock-names = "g1", "g2";
1506 #power-domain-cells = <1>;
1510 compatible = "fsl,imx8mq-pcie";
1513 reg-names = "dbi", "config";
1514 #address-cells = <3>;
1515 #size-cells = <2>;
1517 bus-range = <0x00 0xff>;
1519 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1520 num-lanes = <1>;
1522 interrupt-names = "msi";
1523 #interrupt-cells = <1>;
1524 interrupt-map-mask = <0 0 0 0x7>;
1525 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1529 fsl,max-link-speed = <2>;
1530 linux,pci-domain = <0>;
1531 power-domains = <&pgc_pcie>;
1535 reset-names = "pciephy", "apps", "turnoff";
1536 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1539 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1542 assigned-clock-rates = <250000000>, <100000000>,
1548 compatible = "fsl,imx8mq-pcie";
1551 reg-names = "dbi", "config";
1552 #address-cells = <3>;
1553 #size-cells = <2>;
1556 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1557 num-lanes = <1>;
1559 interrupt-names = "msi";
1560 #interrupt-cells = <1>;
1561 interrupt-map-mask = <0 0 0 0x7>;
1562 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1566 fsl,max-link-speed = <2>;
1567 linux,pci-domain = <1>;
1568 power-domains = <&pgc_pcie>;
1572 reset-names = "pciephy", "apps", "turnoff";
1573 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1576 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1579 assigned-clock-rates = <250000000>, <100000000>,
1584 gic: interrupt-controller@38800000 {
1585 compatible = "arm,gic-v3";
1591 #interrupt-cells = <3>;
1592 interrupt-controller;
1594 interrupt-parent = <&gic>;
1597 ddrc: memory-controller@3d400000 {
1598 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1600 clock-names = "core", "pll", "alt", "apb";
1608 ddr-pmu@3d800000 {
1609 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1611 interrupt-parent = <&gic>;