Lines Matching +full:0 +full:x10000
47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
108 reg = <0x0>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
128 reg = <0x1>;
132 i-cache-size = <0x8000>;
135 d-cache-size = <0x8000>;
146 reg = <0x2>;
150 i-cache-size = <0x8000>;
153 d-cache-size = <0x8000>;
164 reg = <0x3>;
168 i-cache-size = <0x8000>;
171 d-cache-size = <0x8000>;
182 cache-size = <0x100000>;
196 opp-supported-hw = <0xf>, <0x4>;
205 opp-supported-hw = <0xe>, <0x3>;
213 opp-supported-hw = <0xc>, <0x4>;
221 opp-supported-hw = <0x8>, <0x3>;
242 thermal-sensors = <&tmu 0>;
323 soc: soc@0 {
327 ranges = <0x0 0x0 0x0 0x3e000000>;
328 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
334 reg = <0x30000000 0x400000>;
337 ranges = <0x30000000 0x30000000 0x400000>;
340 #sound-dai-cells = <0>;
342 reg = <0x30010000 0x10000>;
348 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
354 #sound-dai-cells = <0>;
356 reg = <0x30030000 0x10000>;
362 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
368 #sound-dai-cells = <0>;
370 reg = <0x30040000 0x10000>;
376 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
382 #sound-dai-cells = <0>;
384 reg = <0x30050000 0x10000>;
390 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
397 reg = <0x30200000 0x10000>;
405 gpio-ranges = <&iomuxc 0 10 30>;
410 reg = <0x30210000 0x10000>;
418 gpio-ranges = <&iomuxc 0 40 21>;
423 reg = <0x30220000 0x10000>;
431 gpio-ranges = <&iomuxc 0 61 26>;
436 reg = <0x30230000 0x10000>;
444 gpio-ranges = <&iomuxc 0 87 32>;
449 reg = <0x30240000 0x10000>;
457 gpio-ranges = <&iomuxc 0 119 30>;
462 reg = <0x30260000 0x10000>;
466 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
467 fsl,tmu-calibration = <0x00000000 0x00000023>,
468 <0x00000001 0x00000029>,
469 <0x00000002 0x0000002f>,
470 <0x00000003 0x00000035>,
471 <0x00000004 0x0000003d>,
472 <0x00000005 0x00000043>,
473 <0x00000006 0x0000004b>,
474 <0x00000007 0x00000051>,
475 <0x00000008 0x00000057>,
476 <0x00000009 0x0000005f>,
477 <0x0000000a 0x00000067>,
478 <0x0000000b 0x0000006f>,
480 <0x00010000 0x0000001b>,
481 <0x00010001 0x00000023>,
482 <0x00010002 0x0000002b>,
483 <0x00010003 0x00000033>,
484 <0x00010004 0x0000003b>,
485 <0x00010005 0x00000043>,
486 <0x00010006 0x0000004b>,
487 <0x00010007 0x00000055>,
488 <0x00010008 0x0000005d>,
489 <0x00010009 0x00000067>,
490 <0x0001000a 0x00000070>,
492 <0x00020000 0x00000017>,
493 <0x00020001 0x00000023>,
494 <0x00020002 0x0000002d>,
495 <0x00020003 0x00000037>,
496 <0x00020004 0x00000041>,
497 <0x00020005 0x0000004b>,
498 <0x00020006 0x00000057>,
499 <0x00020007 0x00000063>,
500 <0x00020008 0x0000006f>,
502 <0x00030000 0x00000015>,
503 <0x00030001 0x00000021>,
504 <0x00030002 0x0000002d>,
505 <0x00030003 0x00000039>,
506 <0x00030004 0x00000045>,
507 <0x00030005 0x00000053>,
508 <0x00030006 0x0000005f>,
509 <0x00030007 0x00000071>;
515 reg = <0x30280000 0x10000>;
523 reg = <0x30290000 0x10000>;
531 reg = <0x302a0000 0x10000>;
539 reg = <0x302c0000 0x10000>;
550 reg = <0x30320000 0x10000>;
561 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
573 reg = <0x30330000 0x10000>;
579 reg = <0x30340000 0x10000>;
584 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
590 reg = <0x30350000 0x10000>;
596 reg = <0x4 0x8>;
600 reg = <0x10 4>;
604 reg = <0x90 6>;
610 reg = <0x30360000 0x10000>;
615 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
616 reg = <0x30370000 0x10000>;
619 compatible = "fsl,sec-v4.0-mon-rtc-lp";
621 offset = <0x34>;
629 compatible = "fsl,sec-v4.0-pwrkey";
642 reg = <0x30380000 0x10000>;
660 assigned-clock-rates = <0>, <0>,
662 <0>,
663 <0>,
664 <0>,
669 <0>,
677 reg = <0x30390000 0x10000>;
684 reg = <0x303a0000 0x10000>;
692 #size-cells = <0>;
694 pgc_mipi: power-domain@0 {
695 #power-domain-cells = <0>;
715 #power-domain-cells = <0>;
721 #power-domain-cells = <0>;
726 #power-domain-cells = <0>;
731 #power-domain-cells = <0>;
736 #power-domain-cells = <0>;
745 #power-domain-cells = <0>;
761 <0>;
765 #power-domain-cells = <0>;
770 #power-domain-cells = <0>;
775 #power-domain-cells = <0>;
780 #power-domain-cells = <0>;
789 reg = <0x30400000 0x400000>;
792 ranges = <0x30400000 0x30400000 0x400000>;
796 reg = <0x30660000 0x10000>;
807 reg = <0x30670000 0x10000>;
818 reg = <0x30680000 0x10000>;
829 reg = <0x30690000 0x10000>;
840 reg = <0x306a0000 0x20000>;
849 reg = <0x30800000 0x400000>;
852 ranges = <0x30800000 0x30800000 0x400000>,
853 <0x08000000 0x08000000 0x10000000>;
857 reg = <0x30810000 0x10000>;
874 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
881 #size-cells = <0>;
883 reg = <0x30820000 0x10000>;
888 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
895 #size-cells = <0>;
897 reg = <0x30830000 0x10000>;
909 #size-cells = <0>;
911 reg = <0x30840000 0x10000>;
924 reg = <0x30860000 0x10000>;
935 reg = <0x30880000 0x10000>;
946 reg = <0x30890000 0x10000>;
956 reg = <0x308a0000 0x10000>;
973 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
979 #sound-dai-cells = <0>;
981 reg = <0x308b0000 0x10000>;
987 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
993 #sound-dai-cells = <0>;
995 reg = <0x308c0000 0x10000>;
1001 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
1007 compatible = "fsl,sec-v4.0";
1010 reg = <0x30900000 0x40000>;
1011 ranges = <0 0x30900000 0x40000>;
1018 compatible = "fsl,sec-v4.0-job-ring";
1019 reg = <0x1000 0x1000>;
1025 compatible = "fsl,sec-v4.0-job-ring";
1026 reg = <0x2000 0x1000>;
1031 compatible = "fsl,sec-v4.0-job-ring";
1032 reg = <0x3000 0x1000>;
1039 reg = <0x30a00000 0x300>;
1053 mux-controls = <&mux 0>;
1066 #size-cells = <0>;
1068 port@0 {
1069 reg = <0>;
1071 #size-cells = <0>;
1072 mipi_dsi_lcdif_in: endpoint@0 {
1073 reg = <0>;
1082 reg = <0x30a00300 0x100>;
1092 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1093 #phy-cells = <0>;
1100 reg = <0x30a20000 0x10000>;
1104 #size-cells = <0>;
1110 reg = <0x30a30000 0x10000>;
1114 #size-cells = <0>;
1120 reg = <0x30a40000 0x10000>;
1124 #size-cells = <0>;
1130 reg = <0x30a50000 0x10000>;
1134 #size-cells = <0>;
1141 reg = <0x30a60000 0x10000>;
1151 reg = <0x30a70000 0x1000>;
1167 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1174 #size-cells = <0>;
1188 reg = <0x30a90000 0x10000>;
1203 reg = <0x30b60000 0x1000>;
1219 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1226 #size-cells = <0>;
1240 reg = <0x30b80000 0x10000>;
1255 reg = <0x30aa0000 0x10000>;
1264 reg = <0x30b40000 0x10000>;
1279 reg = <0x30b50000 0x10000>;
1293 #size-cells = <0>;
1295 reg = <0x30bb0000 0x10000>,
1296 <0x08000000 0x10000000>;
1307 reg = <0x30bd0000 0x10000>;
1318 reg = <0x30be0000 0x10000>;
1338 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1343 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1350 reg = <0x32700000 0x100000>;
1375 reg = <0x32c00000 0x400000>;
1378 ranges = <0x32c00000 0x32c00000 0x400000>;
1382 reg = <0x32e2d000 0x1000>;
1386 fsl,channel = <0>;
1395 reg = <0x38000000 0x40000>;
1414 <800000000>, <800000000>, <0>;
1420 reg = <0x38100000 0x10000>;
1440 reg = <0x381f0040 0x40>;
1446 #phy-cells = <0>;
1452 reg = <0x38200000 0x10000>;
1472 reg = <0x382f0040 0x40>;
1478 #phy-cells = <0>;
1484 reg = <0x38300000 0x10000>;
1492 reg = <0x38310000 0x10000>;
1500 reg = <0x38320000 0x100>;
1511 reg = <0x33800000 0x400000>,
1512 <0x1ff00000 0x80000>;
1517 bus-range = <0x00 0xff>;
1518 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1519 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1524 interrupt-map-mask = <0 0 0 0x7>;
1525 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1526 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1527 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1528 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1530 linux,pci-domain = <0>;
1549 reg = <0x33c00000 0x400000>,
1550 <0x27f00000 0x80000>;
1555 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
1556 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1561 interrupt-map-mask = <0 0 0 0x7>;
1562 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1563 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1564 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1565 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1586 reg = <0x38800000 0x10000>, /* GIC Dist */
1587 <0x38880000 0xc0000>, /* GICR */
1588 <0x31000000 0x2000>, /* GICC */
1589 <0x31010000 0x2000>, /* GICV */
1590 <0x31020000 0x2000>; /* GICH */
1599 reg = <0x3d400000 0x400000>;
1610 reg = <0x3d800000 0x400000>;