Lines Matching +full:mipi +full:- +full:phy +full:- +full:gpr
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a53";
54 clock-latency = <61036>;
56 enable-method = "psci";
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
63 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = <&a53_opp_table>;
67 #cooling-cells = <2>;
72 compatible = "arm,cortex-a53";
74 clock-latency = <61036>;
76 enable-method = "psci";
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
79 i-cache-sets = <256>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
82 d-cache-sets = <128>;
83 next-level-cache = <&A53_L2>;
84 operating-points-v2 = <&a53_opp_table>;
85 #cooling-cells = <2>;
90 compatible = "arm,cortex-a53";
92 clock-latency = <61036>;
94 enable-method = "psci";
95 i-cache-size = <0x8000>;
96 i-cache-line-size = <64>;
97 i-cache-sets = <256>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>;
101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>;
108 compatible = "arm,cortex-a53";
110 clock-latency = <61036>;
112 enable-method = "psci";
113 i-cache-size = <0x8000>;
114 i-cache-line-size = <64>;
115 i-cache-sets = <256>;
116 d-cache-size = <0x8000>;
117 d-cache-line-size = <64>;
118 d-cache-sets = <128>;
119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>;
124 A53_L2: l2-cache0 {
126 cache-level = <2>;
127 cache-size = <0x80000>;
128 cache-line-size = <64>;
129 cache-sets = <512>;
133 a53_opp_table: opp-table {
134 compatible = "operating-points-v2";
135 opp-shared;
137 opp-1200000000 {
138 opp-hz = /bits/ 64 <1200000000>;
139 opp-microvolt = <850000>;
140 opp-supported-hw = <0x8a0>, <0x7>;
141 clock-latency-ns = <150000>;
142 opp-suspend;
145 opp-1600000000 {
146 opp-hz = /bits/ 64 <1600000000>;
147 opp-microvolt = <950000>;
148 opp-supported-hw = <0xa0>, <0x7>;
149 clock-latency-ns = <150000>;
150 opp-suspend;
153 opp-1800000000 {
154 opp-hz = /bits/ 64 <1800000000>;
155 opp-microvolt = <1000000>;
156 opp-supported-hw = <0x20>, <0x3>;
157 clock-latency-ns = <150000>;
158 opp-suspend;
162 osc_32k: clock-osc-32k {
163 compatible = "fixed-clock";
164 #clock-cells = <0>;
165 clock-frequency = <32768>;
166 clock-output-names = "osc_32k";
169 osc_24m: clock-osc-24m {
170 compatible = "fixed-clock";
171 #clock-cells = <0>;
172 clock-frequency = <24000000>;
173 clock-output-names = "osc_24m";
176 clk_ext1: clock-ext1 {
177 compatible = "fixed-clock";
178 #clock-cells = <0>;
179 clock-frequency = <133000000>;
180 clock-output-names = "clk_ext1";
183 clk_ext2: clock-ext2 {
184 compatible = "fixed-clock";
185 #clock-cells = <0>;
186 clock-frequency = <133000000>;
187 clock-output-names = "clk_ext2";
190 clk_ext3: clock-ext3 {
191 compatible = "fixed-clock";
192 #clock-cells = <0>;
193 clock-frequency = <133000000>;
194 clock-output-names = "clk_ext3";
197 clk_ext4: clock-ext4 {
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <133000000>;
201 clock-output-names = "clk_ext4";
204 reserved-memory {
205 #address-cells = <2>;
206 #size-cells = <2>;
211 no-map;
216 compatible = "arm,cortex-a53-pmu";
222 compatible = "arm,psci-1.0";
226 thermal-zones {
227 cpu-thermal {
228 polling-delay-passive = <250>;
229 polling-delay = <2000>;
230 thermal-sensors = <&tmu 0>;
245 cooling-maps {
248 cooling-device =
257 soc-thermal {
258 polling-delay-passive = <250>;
259 polling-delay = <2000>;
260 thermal-sensors = <&tmu 1>;
275 cooling-maps {
278 cooling-device =
289 compatible = "arm,armv8-timer";
294 clock-frequency = <8000000>;
295 arm,no-tick-in-suspend;
299 compatible = "fsl,imx8mp-soc", "simple-bus";
300 #address-cells = <1>;
301 #size-cells = <1>;
303 nvmem-cells = <&imx8mp_uid>;
304 nvmem-cell-names = "soc_unique_id";
307 compatible = "fsl,aips-bus", "simple-bus";
309 #address-cells = <1>;
310 #size-cells = <1>;
314 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
319 gpio-controller;
320 #gpio-cells = <2>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 gpio-ranges = <&iomuxc 0 5 30>;
327 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 gpio-ranges = <&iomuxc 0 35 21>;
340 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
353 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 gpio-ranges = <&iomuxc 0 82 32>;
366 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 gpio-ranges = <&iomuxc 0 114 30>;
379 compatible = "fsl,imx8mp-tmu";
382 #thermal-sensor-cells = <1>;
386 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
394 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
402 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
410 compatible = "fsl,imx8mp-iomuxc";
414 gpr: iomuxc-gpr@30340000 { label
415 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
420 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
424 #address-cells = <1>;
425 #size-cells = <1>;
427 imx8mp_uid: unique-id@420 {
431 cpu_speed_grade: speed-grade@10 {
435 eth_mac1: mac-address@90 {
439 eth_mac2: mac-address@96 {
445 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
451 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
454 snvs_rtc: snvs-rtc-lp {
455 compatible = "fsl,sec-v4.0-mon-rtc-lp";
461 clock-names = "snvs-rtc";
464 snvs_pwrkey: snvs-powerkey {
465 compatible = "fsl,sec-v4.0-pwrkey";
469 clock-names = "snvs-pwrkey";
471 wakeup-source;
475 snvs_lpgpr: snvs-lpgpr {
476 compatible = "fsl,imx8mp-snvs-lpgpr",
477 "fsl,imx7d-snvs-lpgpr";
481 clk: clock-controller@30380000 {
482 compatible = "fsl,imx8mp-ccm";
484 #clock-cells = <1>;
487 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
489 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
498 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
505 assigned-clock-rates = <0>, <0>,
515 src: reset-controller@30390000 {
516 compatible = "fsl,imx8mp-src", "syscon";
519 #reset-cells = <1>;
523 compatible = "fsl,imx8mp-gpc";
525 interrupt-parent = <&gic>;
526 interrupt-controller;
527 #interrupt-cells = <3>;
530 #address-cells = <1>;
531 #size-cells = <0>;
533 pgc_mipi_phy1: power-domain@0 {
534 #power-domain-cells = <0>;
538 pgc_pcie_phy: power-domain@1 {
539 #power-domain-cells = <0>;
543 pgc_usb1_phy: power-domain@2 {
544 #power-domain-cells = <0>;
548 pgc_usb2_phy: power-domain@3 {
549 #power-domain-cells = <0>;
553 pgc_gpu2d: power-domain@6 {
554 #power-domain-cells = <0>;
557 power-domains = <&pgc_gpumix>;
560 pgc_gpumix: power-domain@7 {
561 #power-domain-cells = <0>;
565 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
567 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
569 assigned-clock-rates = <800000000>, <400000000>;
572 pgc_gpu3d: power-domain@9 {
573 #power-domain-cells = <0>;
577 power-domains = <&pgc_gpumix>;
580 pgc_mediamix: power-domain@10 {
581 #power-domain-cells = <0>;
587 pgc_mipi_phy2: power-domain@16 {
588 #power-domain-cells = <0>;
592 pgc_hsiomix: power-domains@17 {
593 #power-domain-cells = <0>;
597 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
598 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
599 assigned-clock-rates = <500000000>;
602 pgc_ispdwp: power-domain@18 {
603 #power-domain-cells = <0>;
608 pgc_vpumix: power-domain@19 {
609 #power-domain-cells = <0>;
614 pgc_vpu_g1: power-domain@20 {
615 #power-domain-cells = <0>;
616 power-domains = <&pgc_vpumix>;
621 pgc_vpu_g2: power-domain@21 {
622 #power-domain-cells = <0>;
623 power-domains = <&pgc_vpumix>;
628 pgc_vpu_vc8000e: power-domain@22 {
629 #power-domain-cells = <0>;
630 power-domains = <&pgc_vpumix>;
639 compatible = "fsl,aips-bus", "simple-bus";
641 #address-cells = <1>;
642 #size-cells = <1>;
646 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
651 clock-names = "ipg", "per";
652 #pwm-cells = <3>;
657 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
662 clock-names = "ipg", "per";
663 #pwm-cells = <3>;
668 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
673 clock-names = "ipg", "per";
674 #pwm-cells = <3>;
679 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
684 clock-names = "ipg", "per";
685 #pwm-cells = <3>;
690 compatible = "nxp,sysctr-timer";
694 clock-names = "per";
699 compatible = "fsl,aips-bus", "simple-bus";
701 #address-cells = <1>;
702 #size-cells = <1>;
706 #address-cells = <1>;
707 #size-cells = <0>;
708 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
713 clock-names = "ipg", "per";
715 dma-names = "rx", "tx";
720 #address-cells = <1>;
721 #size-cells = <0>;
722 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
727 clock-names = "ipg", "per";
729 dma-names = "rx", "tx";
734 #address-cells = <1>;
735 #size-cells = <0>;
736 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
741 clock-names = "ipg", "per";
743 dma-names = "rx", "tx";
748 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
753 clock-names = "ipg", "per";
755 dma-names = "rx", "tx";
760 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
765 clock-names = "ipg", "per";
767 dma-names = "rx", "tx";
772 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
777 clock-names = "ipg", "per";
779 dma-names = "rx", "tx";
784 compatible = "fsl,imx8mp-flexcan";
789 clock-names = "ipg", "per";
790 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
791 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
792 assigned-clock-rates = <40000000>;
793 fsl,clk-source = /bits/ 8 <0>;
794 fsl,stop-mode = <&gpr 0x10 4>;
799 compatible = "fsl,imx8mp-flexcan";
804 clock-names = "ipg", "per";
805 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
806 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
807 assigned-clock-rates = <40000000>;
808 fsl,clk-source = /bits/ 8 <0>;
809 fsl,stop-mode = <&gpr 0x10 5>;
814 compatible = "fsl,sec-v4.0";
815 #address-cells = <1>;
816 #size-cells = <1>;
822 clock-names = "aclk", "ipg";
825 compatible = "fsl,sec-v4.0-job-ring";
832 compatible = "fsl,sec-v4.0-job-ring";
838 compatible = "fsl,sec-v4.0-job-ring";
845 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
846 #address-cells = <1>;
847 #size-cells = <0>;
855 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
856 #address-cells = <1>;
857 #size-cells = <0>;
865 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
866 #address-cells = <1>;
867 #size-cells = <0>;
875 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
876 #address-cells = <1>;
877 #size-cells = <0>;
885 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
890 clock-names = "ipg", "per";
892 dma-names = "rx", "tx";
897 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
901 #mbox-cells = <2>;
905 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
908 #mbox-cells = <2>;
913 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
914 #address-cells = <1>;
915 #size-cells = <0>;
923 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
924 #address-cells = <1>;
925 #size-cells = <0>;
933 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
939 clock-names = "ipg", "ahb", "per";
940 fsl,tuning-start-tap = <20>;
941 fsl,tuning-step = <2>;
942 bus-width = <4>;
947 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
953 clock-names = "ipg", "ahb", "per";
954 fsl,tuning-start-tap = <20>;
955 fsl,tuning-step = <2>;
956 bus-width = <4>;
961 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
967 clock-names = "ipg", "ahb", "per";
968 fsl,tuning-start-tap = <20>;
969 fsl,tuning-step = <2>;
970 bus-width = <4>;
975 compatible = "nxp,imx8mp-fspi";
977 reg-names = "fspi_base", "fspi_mmap";
981 clock-names = "fspi_en", "fspi";
982 assigned-clock-rates = <80000000>;
983 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
984 #address-cells = <1>;
985 #size-cells = <0>;
989 sdma1: dma-controller@30bd0000 {
990 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
995 clock-names = "ipg", "ahb";
996 #dma-cells = <3>;
997 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1001 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1012 clock-names = "ipg", "ahb", "ptp",
1014 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1018 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1022 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1023 fsl,num-tx-queues = <3>;
1024 fsl,num-rx-queues = <3>;
1025 nvmem-cells = <ð_mac1>;
1026 nvmem-cell-names = "mac-address";
1027 fsl,stop-mode = <&gpr 0x10 3>;
1032 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1036 interrupt-names = "macirq", "eth_wake_irq";
1041 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1042 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1045 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1048 assigned-clock-rates = <0>, <100000000>, <125000000>;
1049 nvmem-cells = <ð_mac2>;
1050 nvmem-cell-names = "mac-address";
1051 intf_mode = <&gpr 0x4>;
1057 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1060 #interconnect-cells = <1>;
1061 operating-points-v2 = <&noc_opp_table>;
1063 noc_opp_table: opp-table {
1064 compatible = "operating-points-v2";
1066 opp-200M {
1067 opp-hz = /bits/ 64 <200000000>;
1070 opp-1000M {
1071 opp-hz = /bits/ 64 <1000000000>;
1077 compatible = "fsl,aips-bus", "simple-bus";
1079 #address-cells = <1>;
1080 #size-cells = <1>;
1083 media_blk_ctrl: blk-ctrl@32ec0000 {
1084 compatible = "fsl,imx8mp-media-blk-ctrl",
1087 power-domains = <&pgc_mediamix>,
1097 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1098 "lcdif1", "isi", "mipi-csi2",
1100 "mipi-dsi2";
1110 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1121 clock-names = "apb", "axi", "cam1", "cam2",
1122 "disp1", "disp2", "isp", "phy";
1124 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1126 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1128 assigned-clock-rates = <500000000>, <200000000>;
1130 #power-domain-cells = <1>;
1133 pcie_phy: pcie-phy@32f00000 {
1134 compatible = "fsl,imx8mp-pcie-phy";
1138 reset-names = "pciephy", "perst";
1139 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1140 #phy-cells = <0>;
1144 hsio_blk_ctrl: blk-ctrl@32f10000 {
1145 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1149 clock-names = "usb", "pcie";
1150 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1153 power-domain-names = "bus", "usb", "usb-phy1",
1154 "usb-phy2", "pcie", "pcie-phy";
1159 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
1160 #power-domain-cells = <1>;
1165 compatible = "fsl,imx8mp-pcie";
1167 reg-names = "dbi", "config";
1168 #address-cells = <3>;
1169 #size-cells = <2>;
1171 bus-range = <0x00 0xff>;
1173 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1174 num-lanes = <1>;
1175 num-viewport = <4>;
1177 interrupt-names = "msi";
1178 #interrupt-cells = <1>;
1179 interrupt-map-mask = <0 0 0 0x7>;
1180 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1184 fsl,max-link-speed = <3>;
1185 linux,pci-domain = <0>;
1186 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1189 reset-names = "apps", "turnoff";
1191 phy-names = "pcie-phy";
1203 clock-names = "core", "shader", "bus", "reg";
1204 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1206 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1208 assigned-clock-rates = <800000000>, <800000000>;
1209 power-domains = <&pgc_gpu3d>;
1219 clock-names = "core", "bus", "reg";
1220 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1221 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1222 assigned-clock-rates = <800000000>;
1223 power-domains = <&pgc_gpu2d>;
1226 vpumix_blk_ctrl: blk-ctrl@38330000 {
1227 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1229 #power-domain-cells = <1>;
1230 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1232 power-domain-names = "bus", "g1", "g2", "vc8000e";
1236 clock-names = "g1", "g2", "vc8000e";
1240 interconnect-names = "g1", "g2", "vc8000e";
1243 gic: interrupt-controller@38800000 {
1244 compatible = "arm,gic-v3";
1247 #interrupt-cells = <3>;
1248 interrupt-controller;
1250 interrupt-parent = <&gic>;
1253 edacmc: memory-controller@3d400000 {
1254 compatible = "snps,ddrc-3.80a";
1259 ddr-pmu@3d800000 {
1260 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1265 usb3_phy0: usb-phy@381f0040 {
1266 compatible = "fsl,imx8mp-usb-phy";
1269 clock-names = "phy";
1270 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1271 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1272 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
1273 #phy-cells = <0>;
1278 compatible = "fsl,imx8mp-dwc3";
1283 clock-names = "hsio", "suspend";
1285 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1286 #address-cells = <1>;
1287 #size-cells = <1>;
1288 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1298 clock-names = "bus_early", "ref", "suspend";
1301 phy-names = "usb2-phy", "usb3-phy";
1302 snps,gfladj-refclk-lpm-sel-quirk;
1307 usb3_phy1: usb-phy@382f0040 {
1308 compatible = "fsl,imx8mp-usb-phy";
1311 clock-names = "phy";
1312 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1313 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1314 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
1315 #phy-cells = <0>;
1320 compatible = "fsl,imx8mp-dwc3";
1325 clock-names = "hsio", "suspend";
1327 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1328 #address-cells = <1>;
1329 #size-cells = <1>;
1330 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1340 clock-names = "bus_early", "ref", "suspend";
1343 phy-names = "usb2-phy", "usb3-phy";
1344 snps,gfladj-refclk-lpm-sel-quirk;
1349 compatible = "fsl,imx8mp-dsp";
1351 mbox-names = "txdb0", "txdb1",
1355 memory-region = <&dsp_reserved>;