Lines Matching +full:0 +full:x10000
48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
98 d-cache-size = <0x8000>;
109 reg = <0x3>;
113 i-cache-size = <0x8000>;
116 d-cache-size = <0x8000>;
127 cache-size = <0x80000>;
140 opp-supported-hw = <0x8a0>, <0x7>;
148 opp-supported-hw = <0xa0>, <0x7>;
156 opp-supported-hw = <0x20>, <0x3>;
164 #clock-cells = <0>;
171 #clock-cells = <0>;
178 #clock-cells = <0>;
185 #clock-cells = <0>;
192 #clock-cells = <0>;
199 #clock-cells = <0>;
210 reg = <0 0x92400000 0 0x2000000>;
230 thermal-sensors = <&tmu 0>;
298 soc: soc@0 {
302 ranges = <0x0 0x0 0x0 0x3e000000>;
308 reg = <0x30000000 0x400000>;
315 reg = <0x30200000 0x10000>;
323 gpio-ranges = <&iomuxc 0 5 30>;
328 reg = <0x30210000 0x10000>;
336 gpio-ranges = <&iomuxc 0 35 21>;
341 reg = <0x30220000 0x10000>;
349 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
354 reg = <0x30230000 0x10000>;
362 gpio-ranges = <&iomuxc 0 82 32>;
367 reg = <0x30240000 0x10000>;
375 gpio-ranges = <&iomuxc 0 114 30>;
380 reg = <0x30260000 0x10000>;
387 reg = <0x30280000 0x10000>;
395 reg = <0x30290000 0x10000>;
403 reg = <0x302a0000 0x10000>;
411 reg = <0x30330000 0x10000>;
416 reg = <0x30340000 0x10000>;
421 reg = <0x30350000 0x10000>;
428 reg = <0x8 0x8>;
432 reg = <0x10 4>;
436 reg = <0x90 6>;
440 reg = <0x96 6>;
447 reg = <0x30360000 0x10000>;
451 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
452 reg = <0x30370000 0x10000>;
455 compatible = "fsl,sec-v4.0-mon-rtc-lp";
457 offset = <0x34>;
465 compatible = "fsl,sec-v4.0-pwrkey";
483 reg = <0x30380000 0x10000>;
505 assigned-clock-rates = <0>, <0>,
517 reg = <0x30390000 0x10000>;
524 reg = <0x303a0000 0x1000>;
531 #size-cells = <0>;
533 pgc_mipi_phy1: power-domain@0 {
534 #power-domain-cells = <0>;
539 #power-domain-cells = <0>;
544 #power-domain-cells = <0>;
549 #power-domain-cells = <0>;
554 #power-domain-cells = <0>;
561 #power-domain-cells = <0>;
573 #power-domain-cells = <0>;
581 #power-domain-cells = <0>;
588 #power-domain-cells = <0>;
593 #power-domain-cells = <0>;
603 #power-domain-cells = <0>;
609 #power-domain-cells = <0>;
615 #power-domain-cells = <0>;
622 #power-domain-cells = <0>;
629 #power-domain-cells = <0>;
640 reg = <0x30400000 0x400000>;
647 reg = <0x30660000 0x10000>;
658 reg = <0x30670000 0x10000>;
669 reg = <0x30680000 0x10000>;
680 reg = <0x30690000 0x10000>;
691 reg = <0x306a0000 0x20000>;
700 reg = <0x30800000 0x400000>;
707 #size-cells = <0>;
709 reg = <0x30820000 0x10000>;
714 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
721 #size-cells = <0>;
723 reg = <0x30830000 0x10000>;
735 #size-cells = <0>;
737 reg = <0x30840000 0x10000>;
749 reg = <0x30860000 0x10000>;
754 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
761 reg = <0x30880000 0x10000>;
766 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
773 reg = <0x30890000 0x10000>;
778 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
785 reg = <0x308c0000 0x10000>;
793 fsl,clk-source = /bits/ 8 <0>;
794 fsl,stop-mode = <&gpr 0x10 4>;
800 reg = <0x308d0000 0x10000>;
808 fsl,clk-source = /bits/ 8 <0>;
809 fsl,stop-mode = <&gpr 0x10 5>;
814 compatible = "fsl,sec-v4.0";
817 reg = <0x30900000 0x40000>;
818 ranges = <0 0x30900000 0x40000>;
825 compatible = "fsl,sec-v4.0-job-ring";
826 reg = <0x1000 0x1000>;
832 compatible = "fsl,sec-v4.0-job-ring";
833 reg = <0x2000 0x1000>;
838 compatible = "fsl,sec-v4.0-job-ring";
839 reg = <0x3000 0x1000>;
847 #size-cells = <0>;
848 reg = <0x30a20000 0x10000>;
857 #size-cells = <0>;
858 reg = <0x30a30000 0x10000>;
867 #size-cells = <0>;
868 reg = <0x30a40000 0x10000>;
877 #size-cells = <0>;
878 reg = <0x30a50000 0x10000>;
886 reg = <0x30a60000 0x10000>;
891 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
898 reg = <0x30aa0000 0x10000>;
906 reg = <0x30e60000 0x10000>;
915 #size-cells = <0>;
916 reg = <0x30ad0000 0x10000>;
925 #size-cells = <0>;
926 reg = <0x30ae0000 0x10000>;
934 reg = <0x30b40000 0x10000>;
948 reg = <0x30b50000 0x10000>;
962 reg = <0x30b60000 0x10000>;
976 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
985 #size-cells = <0>;
991 reg = <0x30bd0000 0x10000>;
1002 reg = <0x30be0000 0x10000>;
1022 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1027 fsl,stop-mode = <&gpr 0x10 3>;
1033 reg = <0x30bf0000 0x10000>;
1048 assigned-clock-rates = <0>, <100000000>, <125000000>;
1051 intf_mode = <&gpr 0x4>;
1058 reg = <0x32700000 0x100000>;
1078 reg = <0x32c00000 0x400000>;
1086 reg = <0x32ec0000 0x10000>;
1135 reg = <0x32f00000 0x10000>;
1140 #phy-cells = <0>;
1146 reg = <0x32f10000 0x24>;
1166 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1171 bus-range = <0x00 0xff>;
1172 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1173 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1179 interrupt-map-mask = <0 0 0 0x7>;
1180 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1181 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1182 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1183 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1185 linux,pci-domain = <0>;
1197 reg = <0x38000000 0x8000>;
1214 reg = <0x38008000 0x8000>;
1228 reg = <0x38330000 0x100>;
1245 reg = <0x38800000 0x10000>,
1246 <0x38880000 0xc0000>;
1255 reg = <0x3d400000 0x400000>;
1261 reg = <0x3d800000 0x400000>;
1267 reg = <0x381f0040 0x40>;
1273 #phy-cells = <0>;
1279 reg = <0x32f10100 0x8>,
1280 <0x381f0000 0x20>;
1288 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1294 reg = <0x38100000 0x10000>;
1309 reg = <0x382f0040 0x40>;
1315 #phy-cells = <0>;
1321 reg = <0x32f10108 0x8>,
1322 <0x382f0000 0x20>;
1330 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1336 reg = <0x38200000 0x10000>;
1350 reg = <0x3b6e8000 0x88000>;
1353 mboxes = <&mu2 2 0>, <&mu2 2 1>,
1354 <&mu2 3 0>, <&mu2 3 1>;