Lines Matching +full:imx8mp +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
6 #include "imx8mp.dtsi"
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
29 pinctrl-0 = <&pinctrl_enet_vio>;
30 pinctrl-names = "default";
31 regulator-always-on;
32 regulator-boot-on;
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-name = "eth_vio";
36 vin-supply = <&buck4>;
39 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
40 compatible = "regulator-fixed";
41 enable-active-high;
43 off-on-delay-us = <12000>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
46 regulator-max-microvolt = <3300000>;
47 regulator-min-microvolt = <3300000>;
48 regulator-name = "VDD_3V3_SD";
49 startup-delay-us = <100>;
50 vin-supply = <&buck4>;
55 cpu-supply = <&buck2>;
59 cpu-supply = <&buck2>;
63 cpu-supply = <&buck2>;
67 cpu-supply = <&buck2>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_ecspi1>;
73 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_ecspi2>;
80 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_eqos>;
87 phy-handle = <ðphy0g>;
88 phy-mode = "rgmii-id";
92 compatible = "snps,dwmac-mdio";
93 #address-cells = <1>;
94 #size-cells = <0>;
97 ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
98 compatible = "ethernet-phy-id0007.c110",
99 "ethernet-phy-ieee802.3-c22";
100 interrupt-parent = <&gpio3>;
102 pinctrl-0 = <&pinctrl_ethphy0>;
103 pinctrl-names = "default";
105 reset-assert-us = <1000>;
106 reset-deassert-us = <1000>;
107 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
108 /* Non-default PHY population option. */
112 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
113 compatible = "ethernet-phy-id0022.1642",
114 "ethernet-phy-ieee802.3-c22";
115 interrupt-parent = <&gpio3>;
117 micrel,led-mode = <0>;
118 pinctrl-0 = <&pinctrl_ethphy0>;
119 pinctrl-names = "default";
121 reset-assert-us = <1000>;
122 reset-deassert-us = <1000>;
123 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_fec>;
133 phy-handle = <ðphy1f>;
134 phy-mode = "rgmii";
135 fsl,magic-packet;
139 #address-cells = <1>;
140 #size-cells = <0>;
143 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
144 compatible = "ethernet-phy-id0007.c110",
145 "ethernet-phy-ieee802.3-c22";
146 interrupt-parent = <&gpio4>;
148 pinctrl-0 = <&pinctrl_ethphy1>;
149 pinctrl-names = "default";
151 reset-assert-us = <1000>;
152 reset-deassert-us = <1000>;
153 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
154 /* Non-default PHY population option. */
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_flexcan1>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_flexcan2>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_flexspi>;
178 compatible = "jedec,spi-nor";
180 spi-max-frequency = <80000000>;
181 spi-tx-bus-width = <4>;
182 spi-rx-bus-width = <4>;
187 gpio-line-names =
188 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
189 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
195 gpio-line-names =
197 "", "", "", "DHCOM-K", "", "", "", "",
198 "", "", "", "", "DHCOM-INT", "", "", "",
203 gpio-line-names =
205 "", "", "", "", "", "", "SOM-HW0", "",
206 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
207 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
211 gpio-line-names =
214 "", "", "", "SOM-HW1", "", "", "", "",
215 "", "", "", "DHCOM-D", "", "", "", "";
219 gpio-line-names =
220 "", "", "DHCOM-C", "", "", "", "", "",
222 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
227 clock-frequency = <100000>;
228 pinctrl-names = "default", "gpio";
229 pinctrl-0 = <&pinctrl_i2c3>;
230 pinctrl-1 = <&pinctrl_i2c3_gpio>;
231 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
232 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_pmic>;
240 interrupt-parent = <&gpio1>;
242 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
250 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
251 regulator-compatible = "BUCK1";
252 regulator-min-microvolt = <850000>;
253 regulator-max-microvolt = <1000000>;
254 regulator-ramp-delay = <3125>;
255 regulator-always-on;
256 regulator-boot-on;
260 regulator-compatible = "BUCK2";
261 regulator-min-microvolt = <850000>;
262 regulator-max-microvolt = <1000000>;
263 regulator-ramp-delay = <3125>;
264 regulator-always-on;
265 regulator-boot-on;
269 regulator-compatible = "BUCK4";
270 regulator-min-microvolt = <3300000>;
271 regulator-max-microvolt = <3300000>;
272 regulator-always-on;
273 regulator-boot-on;
277 regulator-compatible = "BUCK5";
278 regulator-min-microvolt = <1800000>;
279 regulator-max-microvolt = <1800000>;
280 regulator-always-on;
281 regulator-boot-on;
285 regulator-compatible = "BUCK6";
286 regulator-min-microvolt = <1100000>;
287 regulator-max-microvolt = <1100000>;
288 regulator-always-on;
289 regulator-boot-on;
293 regulator-compatible = "LDO1";
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <1800000>;
296 regulator-always-on;
297 regulator-boot-on;
301 regulator-compatible = "LDO3";
302 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <1800000>;
304 regulator-always-on;
305 regulator-boot-on;
309 regulator-compatible = "LDO4";
310 regulator-min-microvolt = <3300000>;
311 regulator-max-microvolt = <3300000>;
315 regulator-compatible = "LDO5";
316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <3300000>;
325 #address-cells = <1>;
326 #size-cells = <0>;
364 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_touch>;
367 vio-supply = <&buck4>;
379 interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_rtc>;
392 clock-frequency = <100000>;
393 pinctrl-names = "default", "gpio";
394 pinctrl-0 = <&pinctrl_i2c4>;
395 pinctrl-1 = <&pinctrl_i2c4_gpio>;
396 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
397 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
402 clock-frequency = <100000>;
403 pinctrl-names = "default", "gpio";
404 pinctrl-0 = <&pinctrl_i2c5>;
405 pinctrl-1 = <&pinctrl_i2c5_gpio>;
406 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
407 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
412 pinctrl-0 = <&pinctrl_pwm1>;
413 pinctrl-names = "default";
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_uart1>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_uart2>;
428 uart-has-rtscts;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_uart3>;
435 uart-has-rtscts;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_uart4>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_usb0_vbus>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_usb1_vbus>;
477 pinctrl-names = "default", "state_100mhz", "state_200mhz";
478 pinctrl-0 = <&pinctrl_usdhc1>;
479 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
480 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
481 vmmc-supply = <&buck4>;
482 bus-width = <4>;
483 non-removable;
484 cap-power-off-card;
485 keep-power-in-suspend;
488 #address-cells = <1>;
489 #size-cells = <0>;
493 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
495 * The "host-wake" interrupt output is by default not
499 reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
505 pinctrl-names = "default", "state_100mhz", "state_200mhz";
506 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
507 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
508 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
509 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
510 vmmc-supply = <®_usdhc2_vmmc>;
511 bus-width = <4>;
517 pinctrl-names = "default", "state_100mhz", "state_200mhz";
518 pinctrl-0 = <&pinctrl_usdhc3>;
519 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
520 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
521 vmmc-supply = <&buck4>;
522 vqmmc-supply = <&buck5>;
523 bus-width = <8>;
524 non-removable;
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_wdog>;
531 fsl,ext-reset-output;
536 pinctrl-0 = <&pinctrl_hog_base
543 pinctrl-names = "default";
545 pinctrl_dhcom_a: dhcom-a-grp {
547 /* ENET_QOS_EVENT0-OUT */
552 pinctrl_dhcom_b: dhcom-b-grp {
554 /* ENET_QOS_EVENT0-IN */
559 pinctrl_dhcom_c: dhcom-c-grp {
566 pinctrl_dhcom_d: dhcom-d-grp {
573 pinctrl_dhcom_e: dhcom-e-grp {
580 pinctrl_dhcom_f: dhcom-f-grp {
587 pinctrl_dhcom_g: dhcom-g-grp {
594 pinctrl_dhcom_h: dhcom-h-grp {
601 pinctrl_dhcom_i: dhcom-i-grp {
608 pinctrl_dhcom_j: dhcom-j-grp {
615 pinctrl_dhcom_k: dhcom-k-grp {
622 pinctrl_dhcom_l: dhcom-l-grp {
629 pinctrl_dhcom_int: dhcom-int-grp {
636 pinctrl_hog_base: dhcom-hog-base-grp {
649 pinctrl_ecspi1: dhcom-ecspi1-grp {
658 pinctrl_ecspi2: dhcom-ecspi2-grp {
667 pinctrl_eqos: dhcom-eqos-grp { /* RGMII */
686 pinctrl_enet_vio: dhcom-enet-vio-grp {
692 pinctrl_ethphy0: dhcom-ethphy0-grp {
694 /* ENET1_#RST Reset */
701 pinctrl_ethphy1: dhcom-ethphy1-grp {
703 /* ENET1_#RST Reset */
710 pinctrl_fec: dhcom-fec-grp {
731 pinctrl_flexcan1: dhcom-flexcan1-grp {
738 pinctrl_flexcan2: dhcom-flexcan2-grp {
745 pinctrl_flexspi: dhcom-flexspi-grp {
756 pinctrl_hdmi: dhcom-hdmi-grp {
763 pinctrl_i2c3: dhcom-i2c3-grp {
770 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
777 pinctrl_i2c4: dhcom-i2c4-grp {
784 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
791 pinctrl_i2c5: dhcom-i2c5-grp {
798 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
805 pinctrl_pmic: dhcom-pmic-grp {
812 pinctrl_pwm1: dhcom-pwm1-grp {
818 pinctrl_rtc: dhcom-rtc-grp {
825 pinctrl_touch: dhcom-touch-grp {
832 pinctrl_uart1: dhcom-uart1-grp {
842 pinctrl_uart2: dhcom-uart2-grp {
852 pinctrl_uart3: dhcom-uart3-grp {
861 pinctrl_uart4: dhcom-uart4-grp {
868 pinctrl_usb0_vbus: dhcom-usb0-grp {
874 pinctrl_usb1_vbus: dhcom-usb1-grp {
881 pinctrl_usdhc1: dhcom-usdhc1-grp {
896 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
911 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
926 pinctrl_usdhc2: dhcom-usdhc2-grp {
938 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
950 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
962 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
968 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
974 pinctrl_usdhc3: dhcom-usdhc3-grp {
991 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1008 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1025 pinctrl_wdog: dhcom-wdog-grp {