Lines Matching +full:interrupt +full:- +full:clk
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
45 #address-cells = <1>;
46 #size-cells = <0>;
48 idle-states {
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>;
66 clocks = <&clk IMX8MN_CLK_ARM>;
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>;
87 clocks = <&clk IMX8MN_CLK_ARM>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>;
106 clocks = <&clk IMX8MN_CLK_ARM>;
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>;
125 clocks = <&clk IMX8MN_CLK_ARM>;
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
139 A53_L2: l2-cache0 {
141 cache-level = <2>;
142 cache-size = <0x80000>;
143 cache-line-size = <64>;
144 cache-sets = <512>;
148 a53_opp_table: opp-table {
149 compatible = "operating-points-v2";
150 opp-shared;
152 opp-1200000000 {
153 opp-hz = /bits/ 64 <1200000000>;
154 opp-microvolt = <850000>;
155 opp-supported-hw = <0xb00>, <0x7>;
156 clock-latency-ns = <150000>;
157 opp-suspend;
160 opp-1400000000 {
161 opp-hz = /bits/ 64 <1400000000>;
162 opp-microvolt = <950000>;
163 opp-supported-hw = <0x300>, <0x7>;
164 clock-latency-ns = <150000>;
165 opp-suspend;
168 opp-1500000000 {
169 opp-hz = /bits/ 64 <1500000000>;
170 opp-microvolt = <1000000>;
171 opp-supported-hw = <0x100>, <0x3>;
172 clock-latency-ns = <150000>;
173 opp-suspend;
177 osc_32k: clock-osc-32k {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <32768>;
181 clock-output-names = "osc_32k";
184 osc_24m: clock-osc-24m {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <24000000>;
188 clock-output-names = "osc_24m";
191 clk_ext1: clock-ext1 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext1";
198 clk_ext2: clock-ext2 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext2";
205 clk_ext3: clock-ext3 {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <133000000>;
209 clock-output-names = "clk_ext3";
212 clk_ext4: clock-ext4 {
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <133000000>;
216 clock-output-names = "clk_ext4";
220 compatible = "arm,cortex-a53-pmu";
226 compatible = "arm,psci-1.0";
230 thermal-zones {
231 cpu-thermal {
232 polling-delay-passive = <250>;
233 polling-delay = <2000>;
234 thermal-sensors = <&tmu>;
249 cooling-maps {
252 cooling-device =
263 compatible = "arm,armv8-timer";
268 clock-frequency = <8000000>;
269 arm,no-tick-in-suspend;
273 compatible = "fsl,imx8mn-soc", "simple-bus";
274 #address-cells = <1>;
275 #size-cells = <1>;
277 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
278 nvmem-cells = <&imx8mn_uid>;
279 nvmem-cell-names = "soc_unique_id";
282 compatible = "fsl,aips-bus", "simple-bus";
284 #address-cells = <1>;
285 #size-cells = <1>;
288 spba2: spba-bus@30000000 {
289 compatible = "fsl,spba-bus", "simple-bus";
290 #address-cells = <1>;
291 #size-cells = <1>;
296 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
299 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
300 <&clk IMX8MN_CLK_DUMMY>,
301 <&clk IMX8MN_CLK_SAI2_ROOT>,
302 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
303 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
305 dma-names = "rx", "tx";
310 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
313 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
314 <&clk IMX8MN_CLK_DUMMY>,
315 <&clk IMX8MN_CLK_SAI3_ROOT>,
316 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
317 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
319 dma-names = "rx", "tx";
324 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
327 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
328 <&clk IMX8MN_CLK_DUMMY>,
329 <&clk IMX8MN_CLK_SAI5_ROOT>,
330 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
331 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
333 dma-names = "rx", "tx";
334 fsl,shared-interrupt;
340 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
343 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
344 <&clk IMX8MN_CLK_DUMMY>,
345 <&clk IMX8MN_CLK_SAI6_ROOT>,
346 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
347 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
349 dma-names = "rx", "tx";
353 micfil: audio-controller@30080000 {
354 compatible = "fsl,imx8mm-micfil";
360 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
361 <&clk IMX8MN_CLK_PDM_ROOT>,
362 <&clk IMX8MN_AUDIO_PLL1_OUT>,
363 <&clk IMX8MN_AUDIO_PLL2_OUT>,
364 <&clk IMX8MN_CLK_EXT3>;
365 clock-names = "ipg_clk", "ipg_clk_app",
368 dma-names = "rx";
373 compatible = "fsl,imx35-spdif";
376 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
377 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
378 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
379 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
380 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
382 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
383 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
384 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
385 <&clk IMX8MN_CLK_DUMMY>; /* spba */
386 clock-names = "core", "rxtx0",
392 dma-names = "rx", "tx";
397 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
400 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
401 <&clk IMX8MN_CLK_DUMMY>,
402 <&clk IMX8MN_CLK_SAI7_ROOT>,
403 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
404 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
406 dma-names = "rx", "tx";
411 compatible = "fsl,imx8mn-easrc";
414 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
415 clock-names = "mem";
420 dma-names = "ctx0_rx", "ctx0_tx",
424 firmware-name = "imx/easrc/easrc-imx8mn.bin";
425 fsl,asrc-rate = <8000>;
426 fsl,asrc-format = <2>;
432 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
436 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 gpio-ranges = <&iomuxc 0 10 30>;
445 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
449 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
450 gpio-controller;
451 #gpio-cells = <2>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 gpio-ranges = <&iomuxc 0 40 21>;
458 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
462 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
467 gpio-ranges = <&iomuxc 0 61 26>;
471 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
475 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
476 gpio-controller;
477 #gpio-cells = <2>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
480 gpio-ranges = <&iomuxc 21 108 11>;
484 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
488 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
489 gpio-controller;
490 #gpio-cells = <2>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
493 gpio-ranges = <&iomuxc 0 119 30>;
497 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
499 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
500 #thermal-sensor-cells = <0>;
504 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
507 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
512 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
515 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
520 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
523 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
527 sdma3: dma-controller@302b0000 {
528 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
531 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
532 <&clk IMX8MN_CLK_SDMA3_ROOT>;
533 clock-names = "ipg", "ahb";
534 #dma-cells = <3>;
535 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
538 sdma2: dma-controller@302c0000 {
539 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
542 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
543 <&clk IMX8MN_CLK_SDMA2_ROOT>;
544 clock-names = "ipg", "ahb";
545 #dma-cells = <3>;
546 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
550 compatible = "fsl,imx8mn-iomuxc";
554 gpr: iomuxc-gpr@30340000 {
555 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
560 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
562 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
563 #address-cells = <1>;
564 #size-cells = <1>;
566 imx8mn_uid: unique-id@410 {
570 cpu_speed_grade: speed-grade@10 {
574 fec_mac_address: mac-address@90 {
580 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
586 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
589 snvs_rtc: snvs-rtc-lp {
590 compatible = "fsl,sec-v4.0-mon-rtc-lp";
595 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
596 clock-names = "snvs-rtc";
599 snvs_pwrkey: snvs-powerkey {
600 compatible = "fsl,sec-v4.0-pwrkey";
603 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
604 clock-names = "snvs-pwrkey";
606 wakeup-source;
611 clk: clock-controller@30380000 { label
612 compatible = "fsl,imx8mn-ccm";
614 #clock-cells = <1>;
617 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
619 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
620 <&clk IMX8MN_CLK_A53_CORE>,
621 <&clk IMX8MN_CLK_NOC>,
622 <&clk IMX8MN_CLK_AUDIO_AHB>,
623 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
624 <&clk IMX8MN_SYS_PLL3>,
625 <&clk IMX8MN_AUDIO_PLL1>,
626 <&clk IMX8MN_AUDIO_PLL2>;
627 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
628 <&clk IMX8MN_ARM_PLL_OUT>,
629 <&clk IMX8MN_SYS_PLL3_OUT>,
630 <&clk IMX8MN_SYS_PLL1_800M>;
631 assigned-clock-rates = <0>, <0>, <0>,
639 src: reset-controller@30390000 {
640 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
643 #reset-cells = <1>;
647 compatible = "fsl,imx8mn-gpc";
649 interrupt-parent = <&gic>;
653 #address-cells = <1>;
654 #size-cells = <0>;
656 pgc_hsiomix: power-domain@0 {
657 #power-domain-cells = <0>;
659 clocks = <&clk IMX8MN_CLK_USB_BUS>;
662 pgc_otg1: power-domain@1 {
663 #power-domain-cells = <0>;
667 pgc_gpumix: power-domain@2 {
668 #power-domain-cells = <0>;
670 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
671 <&clk IMX8MN_CLK_GPU_SHADER>,
672 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
673 <&clk IMX8MN_CLK_GPU_AHB>;
676 pgc_dispmix: power-domain@3 {
677 #power-domain-cells = <0>;
679 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
680 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
683 pgc_mipi: power-domain@4 {
684 #power-domain-cells = <0>;
686 power-domains = <&pgc_dispmix>;
693 compatible = "fsl,aips-bus", "simple-bus";
695 #address-cells = <1>;
696 #size-cells = <1>;
700 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
703 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
704 <&clk IMX8MN_CLK_PWM1_ROOT>;
705 clock-names = "ipg", "per";
706 #pwm-cells = <3>;
711 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
714 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
715 <&clk IMX8MN_CLK_PWM2_ROOT>;
716 clock-names = "ipg", "per";
717 #pwm-cells = <3>;
722 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
725 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
726 <&clk IMX8MN_CLK_PWM3_ROOT>;
727 clock-names = "ipg", "per";
728 #pwm-cells = <3>;
733 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
736 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
737 <&clk IMX8MN_CLK_PWM4_ROOT>;
738 clock-names = "ipg", "per";
739 #pwm-cells = <3>;
744 compatible = "nxp,sysctr-timer";
748 clock-names = "per";
753 compatible = "fsl,aips-bus", "simple-bus";
755 #address-cells = <1>;
756 #size-cells = <1>;
759 spba1: spba-bus@30800000 {
760 compatible = "fsl,spba-bus", "simple-bus";
761 #address-cells = <1>;
762 #size-cells = <1>;
767 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
768 #address-cells = <1>;
769 #size-cells = <0>;
772 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
773 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
774 clock-names = "ipg", "per";
776 dma-names = "rx", "tx";
781 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
782 #address-cells = <1>;
783 #size-cells = <0>;
786 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
787 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
788 clock-names = "ipg", "per";
790 dma-names = "rx", "tx";
795 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
796 #address-cells = <1>;
797 #size-cells = <0>;
800 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
801 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
802 clock-names = "ipg", "per";
804 dma-names = "rx", "tx";
809 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
812 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
813 <&clk IMX8MN_CLK_UART1_ROOT>;
814 clock-names = "ipg", "per";
816 dma-names = "rx", "tx";
821 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
824 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
825 <&clk IMX8MN_CLK_UART3_ROOT>;
826 clock-names = "ipg", "per";
828 dma-names = "rx", "tx";
833 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
836 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
837 <&clk IMX8MN_CLK_UART2_ROOT>;
838 clock-names = "ipg", "per";
844 compatible = "fsl,sec-v4.0";
845 #address-cells = <1>;
846 #size-cells = <1>;
850 clocks = <&clk IMX8MN_CLK_AHB>,
851 <&clk IMX8MN_CLK_IPG_ROOT>;
852 clock-names = "aclk", "ipg";
855 compatible = "fsl,sec-v4.0-job-ring";
862 compatible = "fsl,sec-v4.0-job-ring";
868 compatible = "fsl,sec-v4.0-job-ring";
875 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
876 #address-cells = <1>;
877 #size-cells = <0>;
880 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
885 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
886 #address-cells = <1>;
887 #size-cells = <0>;
890 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
895 #address-cells = <1>;
896 #size-cells = <0>;
897 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
900 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
905 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
906 #address-cells = <1>;
907 #size-cells = <0>;
910 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
915 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
918 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
919 <&clk IMX8MN_CLK_UART4_ROOT>;
920 clock-names = "ipg", "per";
922 dma-names = "rx", "tx";
927 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
930 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
931 #mbox-cells = <2>;
935 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
938 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
939 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
940 <&clk IMX8MN_CLK_USDHC1_ROOT>;
941 clock-names = "ipg", "ahb", "per";
942 fsl,tuning-start-tap = <20>;
943 fsl,tuning-step = <2>;
944 bus-width = <4>;
949 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
952 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
953 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
954 <&clk IMX8MN_CLK_USDHC2_ROOT>;
955 clock-names = "ipg", "ahb", "per";
956 fsl,tuning-start-tap = <20>;
957 fsl,tuning-step = <2>;
958 bus-width = <4>;
963 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
966 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
967 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
968 <&clk IMX8MN_CLK_USDHC3_ROOT>;
969 clock-names = "ipg", "ahb", "per";
970 fsl,tuning-start-tap = <20>;
971 fsl,tuning-step = <2>;
972 bus-width = <4>;
977 #address-cells = <1>;
978 #size-cells = <0>;
979 compatible = "nxp,imx8mm-fspi";
981 reg-names = "fspi_base", "fspi_mmap";
983 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
984 <&clk IMX8MN_CLK_QSPI_ROOT>;
985 clock-names = "fspi_en", "fspi";
989 sdma1: dma-controller@30bd0000 {
990 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
993 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
994 <&clk IMX8MN_CLK_AHB>;
995 clock-names = "ipg", "ahb";
996 #dma-cells = <3>;
997 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1001 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1007 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
1008 <&clk IMX8MN_CLK_ENET1_ROOT>,
1009 <&clk IMX8MN_CLK_ENET_TIMER>,
1010 <&clk IMX8MN_CLK_ENET_REF>,
1011 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1012 clock-names = "ipg", "ahb", "ptp",
1014 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1015 <&clk IMX8MN_CLK_ENET_TIMER>,
1016 <&clk IMX8MN_CLK_ENET_REF>,
1017 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1018 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1019 <&clk IMX8MN_SYS_PLL2_100M>,
1020 <&clk IMX8MN_SYS_PLL2_125M>,
1021 <&clk IMX8MN_SYS_PLL2_50M>;
1022 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1023 fsl,num-tx-queues = <3>;
1024 fsl,num-rx-queues = <3>;
1025 nvmem-cells = <&fec_mac_address>;
1026 nvmem-cell-names = "mac-address";
1027 fsl,stop-mode = <&gpr 0x10 3>;
1034 compatible = "fsl,aips-bus", "simple-bus";
1036 #address-cells = <1>;
1037 #size-cells = <1>;
1040 disp_blk_ctrl: blk-ctrl@32e28000 {
1041 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1043 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1046 power-domain-names = "bus", "isi",
1047 "lcdif", "mipi-dsi",
1048 "mipi-csi";
1049 clocks = <&clk IMX8MN_CLK_DISP_AXI>,
1050 <&clk IMX8MN_CLK_DISP_APB>,
1051 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1052 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1053 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1054 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1055 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1056 <&clk IMX8MN_CLK_DSI_CORE>,
1057 <&clk IMX8MN_CLK_DSI_PHY_REF>,
1058 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1059 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
1060 clock-names = "disp_axi", "disp_apb",
1062 "lcdif-axi", "lcdif-apb", "lcdif-pix",
1063 "dsi-pclk", "dsi-ref",
1064 "csi-aclk", "csi-pclk";
1065 #power-domain-cells = <1>;
1069 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
1072 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
1073 clock-names = "usb1_ctrl_root_clk";
1074 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1075 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1078 power-domains = <&pgc_hsiomix>;
1083 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
1084 #index-cells = <1>;
1089 dma_apbh: dma-controller@33000000 {
1090 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1096 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1097 #dma-cells = <1>;
1098 dma-channels = <4>;
1099 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1102 gpmi: nand-controller@33002000 {
1103 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1107 reg-names = "gpmi-nand", "bch";
1109 interrupt-names = "bch";
1110 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1111 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1112 clock-names = "gpmi_io", "gpmi_bch_apb";
1114 dma-names = "rx-tx";
1122 clocks = <&clk IMX8MN_CLK_GPU_AHB>,
1123 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
1124 <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
1125 <&clk IMX8MN_CLK_GPU_SHADER>;
1126 clock-names = "reg", "bus", "core", "shader";
1127 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1128 <&clk IMX8MN_CLK_GPU_SHADER>,
1129 <&clk IMX8MN_CLK_GPU_AXI>,
1130 <&clk IMX8MN_CLK_GPU_AHB>,
1131 <&clk IMX8MN_GPU_PLL>;
1132 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1133 <&clk IMX8MN_GPU_PLL_OUT>,
1134 <&clk IMX8MN_SYS_PLL1_800M>,
1135 <&clk IMX8MN_SYS_PLL1_800M>;
1136 assigned-clock-rates = <400000000>,
1141 power-domains = <&pgc_gpumix>;
1144 gic: interrupt-controller@38800000 {
1145 compatible = "arm,gic-v3";
1148 #interrupt-cells = <3>;
1149 interrupt-controller;
1153 ddrc: memory-controller@3d400000 {
1154 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1156 clock-names = "core", "pll", "alt", "apb";
1157 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1158 <&clk IMX8MN_DRAM_PLL>,
1159 <&clk IMX8MN_CLK_DRAM_ALT>,
1160 <&clk IMX8MN_CLK_DRAM_APB>;
1163 ddr-pmu@3d800000 {
1164 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1171 #phy-cells = <0>;
1172 compatible = "usb-nop-xceiv";
1173 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1174 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1175 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1176 clock-names = "main_clk";
1177 power-domains = <&pgc_otg1>;