Lines Matching +full:0 +full:x10000
46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
123 reg = <0x3>;
127 i-cache-size = <0x8000>;
130 d-cache-size = <0x8000>;
142 cache-size = <0x80000>;
155 opp-supported-hw = <0xb00>, <0x7>;
163 opp-supported-hw = <0x300>, <0x7>;
171 opp-supported-hw = <0x100>, <0x3>;
179 #clock-cells = <0>;
186 #clock-cells = <0>;
193 #clock-cells = <0>;
200 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
272 soc: soc@0 {
276 ranges = <0x0 0x0 0x0 0x3e000000>;
277 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
283 reg = <0x30000000 0x400000>;
292 reg = <0x30000000 0x100000>;
297 reg = <0x30020000 0x10000>;
304 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
311 reg = <0x30030000 0x10000>;
318 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
325 reg = <0x30050000 0x10000>;
332 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
335 fsl,dataline = <0 0xf 0xf>;
341 reg = <0x30060000 0x10000>;
348 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
355 reg = <0x30080000 0x10000>;
367 dmas = <&sdma2 24 25 0x80000000>;
374 reg = <0x30090000 0x10000>;
391 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
398 reg = <0x300b0000 0x10000>;
405 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
412 reg = <0x300c0000 0x10000>;
416 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
417 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
418 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
419 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
433 reg = <0x30200000 0x10000>;
441 gpio-ranges = <&iomuxc 0 10 30>;
446 reg = <0x30210000 0x10000>;
454 gpio-ranges = <&iomuxc 0 40 21>;
459 reg = <0x30220000 0x10000>;
467 gpio-ranges = <&iomuxc 0 61 26>;
472 reg = <0x30230000 0x10000>;
485 reg = <0x30240000 0x10000>;
493 gpio-ranges = <&iomuxc 0 119 30>;
498 reg = <0x30260000 0x10000>;
500 #thermal-sensor-cells = <0>;
505 reg = <0x30280000 0x10000>;
513 reg = <0x30290000 0x10000>;
521 reg = <0x302a0000 0x10000>;
529 reg = <0x302b0000 0x10000>;
540 reg = <0x302c0000 0x10000>;
551 reg = <0x30330000 0x10000>;
556 reg = <0x30340000 0x10000>;
561 reg = <0x30350000 0x10000>;
567 reg = <0x4 0x8>;
571 reg = <0x10 4>;
575 reg = <0x90 6>;
582 reg = <0x30360000 0x10000>;
586 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
587 reg = <0x30370000 0x10000>;
590 compatible = "fsl,sec-v4.0-mon-rtc-lp";
592 offset = <0x34>;
600 compatible = "fsl,sec-v4.0-pwrkey";
613 reg = <0x30380000 0x10000>;
631 assigned-clock-rates = <0>, <0>, <0>,
641 reg = <0x30390000 0x10000>;
648 reg = <0x303a0000 0x10000>;
654 #size-cells = <0>;
656 pgc_hsiomix: power-domain@0 {
657 #power-domain-cells = <0>;
663 #power-domain-cells = <0>;
668 #power-domain-cells = <0>;
677 #power-domain-cells = <0>;
684 #power-domain-cells = <0>;
694 reg = <0x30400000 0x400000>;
701 reg = <0x30660000 0x10000>;
712 reg = <0x30670000 0x10000>;
723 reg = <0x30680000 0x10000>;
734 reg = <0x30690000 0x10000>;
745 reg = <0x306a0000 0x20000>;
754 reg = <0x30800000 0x400000>;
763 reg = <0x30800000 0x100000>;
769 #size-cells = <0>;
770 reg = <0x30820000 0x10000>;
775 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
783 #size-cells = <0>;
784 reg = <0x30830000 0x10000>;
797 #size-cells = <0>;
798 reg = <0x30840000 0x10000>;
810 reg = <0x30860000 0x10000>;
815 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
822 reg = <0x30880000 0x10000>;
827 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
834 reg = <0x30890000 0x10000>;
844 compatible = "fsl,sec-v4.0";
847 reg = <0x30900000 0x40000>;
848 ranges = <0 0x30900000 0x40000>;
855 compatible = "fsl,sec-v4.0-job-ring";
856 reg = <0x1000 0x1000>;
862 compatible = "fsl,sec-v4.0-job-ring";
863 reg = <0x2000 0x1000>;
868 compatible = "fsl,sec-v4.0-job-ring";
869 reg = <0x3000 0x1000>;
877 #size-cells = <0>;
878 reg = <0x30a20000 0x10000>;
887 #size-cells = <0>;
888 reg = <0x30a30000 0x10000>;
896 #size-cells = <0>;
898 reg = <0x30a40000 0x10000>;
907 #size-cells = <0>;
908 reg = <0x30a50000 0x10000>;
916 reg = <0x30a60000 0x10000>;
921 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
928 reg = <0x30aa0000 0x10000>;
936 reg = <0x30b40000 0x10000>;
950 reg = <0x30b50000 0x10000>;
964 reg = <0x30b60000 0x10000>;
978 #size-cells = <0>;
980 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
991 reg = <0x30bd0000 0x10000>;
1002 reg = <0x30be0000 0x10000>;
1022 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1027 fsl,stop-mode = <&gpr 0x10 3>;
1035 reg = <0x32c00000 0x400000>;
1042 reg = <0x32e28000 0x100>;
1070 reg = <0x32e40000 0x200>;
1077 fsl,usbmisc = <&usbmisc1 0>;
1085 reg = <0x32e40200 0x200>;
1091 reg = <0x33000000 0x2000>;
1105 #size-cells = <0>;
1106 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1113 dmas = <&dma_apbh 0>;
1120 reg = <0x38000000 0x8000>;
1146 reg = <0x38800000 0x10000>,
1147 <0x38880000 0xc0000>;
1155 reg = <0x3d400000 0x400000>;
1165 reg = <0x3d800000 0x400000>;
1171 #phy-cells = <0>;