Lines Matching +full:clk +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2020-2021 TQ-Systems GmbH
6 /dts-v1/;
8 #include "imx8mn-tqma8mqnl.dtsi"
12 model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx";
13 compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
24 reg_usdhc2_vmmc: regulator-vmmc {
25 compatible = "regulator-fixed";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
28 regulator-name = "VSD_3V3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
32 enable-active-high;
33 startup-delay-us = <100>;
34 off-on-delay-us = <12000>;
38 /* Located on TQMa8MxML-ADAP */
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_usb0hub_sel>;
43 sel-usb-hub-hog {
44 gpio-hog;
46 output-high;
54 gpio-controller;
55 #gpio-cells = <2>;
56 vcc-supply = <®_vcc_3v3>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_expander2>;
59 interrupt-parent = <&gpio1>;
61 interrupt-controller;
62 #interrupt-cells = <2>;
67 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
68 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
69 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
70 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,
71 <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>,
72 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>,
73 <&clk IMX8MN_AUDIO_PLL2_OUT>;
77 clock-names = "mclk";
78 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
83 disable-over-current;
84 power-active-high;
90 fsl,pins = <MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000146>,
97 fsl,pins = <MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x00000146>,
104 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x94>;
108 fsl,pins = <MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002>,
125 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x84>,
131 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x84>,
136 fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001C4>,
141 fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001C4>,
146 fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001C4>,
151 fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001C4>,
156 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x14>;
160 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x14>;
164 fsl,pins = <MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x94>,
174 fsl,pins = <MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x16>,
179 fsl,pins = <MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x16>,
184 fsl,pins = <MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x16>,
189 fsl,pins = <MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x16>,
193 pinctrl_usb0hub_sel: usb0hub-selgrp {
195 fsl,pins = <MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x84>;
199 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>,
205 fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
214 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
215 fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
224 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
225 fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
234 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
235 fsl,pins = <MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x84>;