Lines Matching +full:csi +full:- +full:bridge
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
45 #address-cells = <1>;
46 #size-cells = <0>;
48 idle-states {
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>; /* two CLK32 periods */
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>; /* two CLK32 periods */
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>; /* two CLK32 periods */
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>; /* two CLK32 periods */
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
139 A53_L2: l2-cache0 {
141 cache-level = <2>;
142 cache-size = <0x80000>;
143 cache-line-size = <64>;
144 cache-sets = <512>;
148 a53_opp_table: opp-table {
149 compatible = "operating-points-v2";
150 opp-shared;
152 opp-1200000000 {
153 opp-hz = /bits/ 64 <1200000000>;
154 opp-microvolt = <850000>;
155 opp-supported-hw = <0xe>, <0x7>;
156 clock-latency-ns = <150000>;
157 opp-suspend;
160 opp-1600000000 {
161 opp-hz = /bits/ 64 <1600000000>;
162 opp-microvolt = <950000>;
163 opp-supported-hw = <0xc>, <0x7>;
164 clock-latency-ns = <150000>;
165 opp-suspend;
168 opp-1800000000 {
169 opp-hz = /bits/ 64 <1800000000>;
170 opp-microvolt = <1000000>;
171 opp-supported-hw = <0x8>, <0x3>;
172 clock-latency-ns = <150000>;
173 opp-suspend;
177 osc_32k: clock-osc-32k {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <32768>;
181 clock-output-names = "osc_32k";
184 osc_24m: clock-osc-24m {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <24000000>;
188 clock-output-names = "osc_24m";
191 clk_ext1: clock-ext1 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext1";
198 clk_ext2: clock-ext2 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext2";
205 clk_ext3: clock-ext3 {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <133000000>;
209 clock-output-names = "clk_ext3";
212 clk_ext4: clock-ext4 {
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <133000000>;
216 clock-output-names = "clk_ext4";
220 compatible = "arm,psci-1.0";
225 compatible = "arm,cortex-a53-pmu";
231 compatible = "arm,armv8-timer";
233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
236 clock-frequency = <8000000>;
237 arm,no-tick-in-suspend;
240 thermal-zones {
241 cpu-thermal {
242 polling-delay-passive = <250>;
243 polling-delay = <2000>;
244 thermal-sensors = <&tmu>;
259 cooling-maps {
262 cooling-device =
273 #phy-cells = <0>;
274 compatible = "usb-nop-xceiv";
276 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
277 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
278 clock-names = "main_clk";
279 power-domains = <&pgc_otg1>;
283 #phy-cells = <0>;
284 compatible = "usb-nop-xceiv";
286 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
287 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
288 clock-names = "main_clk";
289 power-domains = <&pgc_otg2>;
293 compatible = "fsl,imx8mm-soc", "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
297 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
298 nvmem-cells = <&imx8mm_uid>;
299 nvmem-cell-names = "soc_unique_id";
302 compatible = "fsl,aips-bus", "simple-bus";
304 #address-cells = <1>;
305 #size-cells = <1>;
308 spba2: spba-bus@30000000 {
309 compatible = "fsl,spba-bus", "simple-bus";
310 #address-cells = <1>;
311 #size-cells = <1>;
316 #sound-dai-cells = <0>;
317 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
323 clock-names = "bus", "mclk1", "mclk2", "mclk3";
325 dma-names = "rx", "tx";
330 #sound-dai-cells = <0>;
331 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
337 clock-names = "bus", "mclk1", "mclk2", "mclk3";
339 dma-names = "rx", "tx";
344 #sound-dai-cells = <0>;
345 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
351 clock-names = "bus", "mclk1", "mclk2", "mclk3";
353 dma-names = "rx", "tx";
358 #sound-dai-cells = <0>;
359 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
365 clock-names = "bus", "mclk1", "mclk2", "mclk3";
367 dma-names = "rx", "tx";
372 #sound-dai-cells = <0>;
373 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
379 clock-names = "bus", "mclk1", "mclk2", "mclk3";
381 dma-names = "rx", "tx";
385 micfil: audio-controller@30080000 {
386 compatible = "fsl,imx8mm-micfil";
397 clock-names = "ipg_clk", "ipg_clk_app",
400 dma-names = "rx";
405 compatible = "fsl,imx35-spdif";
418 clock-names = "core", "rxtx0",
424 dma-names = "rx", "tx";
430 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
435 gpio-controller;
436 #gpio-cells = <2>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 gpio-ranges = <&iomuxc 0 10 30>;
443 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
448 gpio-controller;
449 #gpio-cells = <2>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 gpio-ranges = <&iomuxc 0 40 21>;
456 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
461 gpio-controller;
462 #gpio-cells = <2>;
463 interrupt-controller;
464 #interrupt-cells = <2>;
465 gpio-ranges = <&iomuxc 0 61 26>;
469 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
474 gpio-controller;
475 #gpio-cells = <2>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 gpio-ranges = <&iomuxc 0 87 32>;
482 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
487 gpio-controller;
488 #gpio-cells = <2>;
489 interrupt-controller;
490 #interrupt-cells = <2>;
491 gpio-ranges = <&iomuxc 0 119 30>;
495 compatible = "fsl,imx8mm-tmu";
498 #thermal-sensor-cells = <0>;
502 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
510 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
518 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
525 sdma2: dma-controller@302c0000 {
526 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
531 clock-names = "ipg", "ahb";
532 #dma-cells = <3>;
533 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
536 sdma3: dma-controller@302b0000 {
537 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
542 clock-names = "ipg", "ahb";
543 #dma-cells = <3>;
544 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
548 compatible = "fsl,imx8mm-iomuxc";
552 gpr: iomuxc-gpr@30340000 {
553 compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
558 compatible = "fsl,imx8mm-ocotp", "syscon";
562 #address-cells = <1>;
563 #size-cells = <1>;
565 imx8mm_uid: unique-id@410 {
569 cpu_speed_grade: speed-grade@10 {
573 fec_mac_address: mac-address@90 {
579 compatible = "fsl,imx8mm-anatop", "syscon";
584 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
587 snvs_rtc: snvs-rtc-lp {
588 compatible = "fsl,sec-v4.0-mon-rtc-lp";
594 clock-names = "snvs-rtc";
597 snvs_pwrkey: snvs-powerkey {
598 compatible = "fsl,sec-v4.0-pwrkey";
602 clock-names = "snvs-pwrkey";
604 wakeup-source;
608 snvs_lpgpr: snvs-lpgpr {
609 compatible = "fsl,imx8mm-snvs-lpgpr",
610 "fsl,imx7d-snvs-lpgpr";
614 clk: clock-controller@30380000 {
615 compatible = "fsl,imx8mm-ccm";
617 #clock-cells = <1>;
620 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
622 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
630 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
634 assigned-clock-rates = <0>, <0>, <0>,
642 src: reset-controller@30390000 {
643 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
646 #reset-cells = <1>;
650 compatible = "fsl,imx8mm-gpc";
653 interrupt-parent = <&gic>;
654 interrupt-controller;
655 #interrupt-cells = <3>;
658 #address-cells = <1>;
659 #size-cells = <0>;
661 pgc_hsiomix: power-domain@0 {
662 #power-domain-cells = <0>;
665 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
666 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
669 pgc_pcie: power-domain@1 {
670 #power-domain-cells = <0>;
672 power-domains = <&pgc_hsiomix>;
676 pgc_otg1: power-domain@2 {
677 #power-domain-cells = <0>;
681 pgc_otg2: power-domain@3 {
682 #power-domain-cells = <0>;
686 pgc_gpumix: power-domain@4 {
687 #power-domain-cells = <0>;
691 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
693 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
695 assigned-clock-rates = <800000000>, <400000000>;
698 pgc_gpu: power-domain@5 {
699 #power-domain-cells = <0>;
706 power-domains = <&pgc_gpumix>;
709 pgc_vpumix: power-domain@6 {
710 #power-domain-cells = <0>;
713 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
714 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
717 pgc_vpu_g1: power-domain@7 {
718 #power-domain-cells = <0>;
722 pgc_vpu_g2: power-domain@8 {
723 #power-domain-cells = <0>;
727 pgc_vpu_h1: power-domain@9 {
728 #power-domain-cells = <0>;
732 pgc_dispmix: power-domain@10 {
733 #power-domain-cells = <0>;
737 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
739 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
741 assigned-clock-rates = <500000000>, <200000000>;
744 pgc_mipi: power-domain@11 {
745 #power-domain-cells = <0>;
753 compatible = "fsl,aips-bus", "simple-bus";
755 #address-cells = <1>;
756 #size-cells = <1>;
760 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
765 clock-names = "ipg", "per";
766 #pwm-cells = <3>;
771 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
776 clock-names = "ipg", "per";
777 #pwm-cells = <3>;
782 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
787 clock-names = "ipg", "per";
788 #pwm-cells = <3>;
793 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
798 clock-names = "ipg", "per";
799 #pwm-cells = <3>;
804 compatible = "nxp,sysctr-timer";
808 clock-names = "per";
813 compatible = "fsl,aips-bus", "simple-bus";
815 #address-cells = <1>;
816 #size-cells = <1>;
820 spba1: spba-bus@30800000 {
821 compatible = "fsl,spba-bus", "simple-bus";
822 #address-cells = <1>;
823 #size-cells = <1>;
828 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
829 #address-cells = <1>;
830 #size-cells = <0>;
835 clock-names = "ipg", "per";
837 dma-names = "rx", "tx";
842 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
843 #address-cells = <1>;
844 #size-cells = <0>;
849 clock-names = "ipg", "per";
851 dma-names = "rx", "tx";
856 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
857 #address-cells = <1>;
858 #size-cells = <0>;
863 clock-names = "ipg", "per";
865 dma-names = "rx", "tx";
870 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
875 clock-names = "ipg", "per";
877 dma-names = "rx", "tx";
882 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
887 clock-names = "ipg", "per";
889 dma-names = "rx", "tx";
894 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
899 clock-names = "ipg", "per";
905 compatible = "fsl,sec-v4.0";
906 #address-cells = <1>;
907 #size-cells = <1>;
913 clock-names = "aclk", "ipg";
916 compatible = "fsl,sec-v4.0-job-ring";
923 compatible = "fsl,sec-v4.0-job-ring";
929 compatible = "fsl,sec-v4.0-job-ring";
936 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
937 #address-cells = <1>;
938 #size-cells = <0>;
946 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
947 #address-cells = <1>;
948 #size-cells = <0>;
956 #address-cells = <1>;
957 #size-cells = <0>;
958 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
966 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
967 #address-cells = <1>;
968 #size-cells = <0>;
976 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
981 clock-names = "ipg", "per";
983 dma-names = "rx", "tx";
988 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
992 #mbox-cells = <2>;
996 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1002 clock-names = "ipg", "ahb", "per";
1003 fsl,tuning-start-tap = <20>;
1004 fsl,tuning-step = <2>;
1005 bus-width = <4>;
1010 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1016 clock-names = "ipg", "ahb", "per";
1017 fsl,tuning-start-tap = <20>;
1018 fsl,tuning-step = <2>;
1019 bus-width = <4>;
1024 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1030 clock-names = "ipg", "ahb", "per";
1031 fsl,tuning-start-tap = <20>;
1032 fsl,tuning-step = <2>;
1033 bus-width = <4>;
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 compatible = "nxp,imx8mm-fspi";
1042 reg-names = "fspi_base", "fspi_mmap";
1046 clock-names = "fspi_en", "fspi";
1050 sdma1: dma-controller@30bd0000 {
1051 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1056 clock-names = "ipg", "ahb";
1057 #dma-cells = <3>;
1058 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1062 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1073 clock-names = "ipg", "ahb", "ptp",
1075 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1079 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1083 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1084 fsl,num-tx-queues = <3>;
1085 fsl,num-rx-queues = <3>;
1086 nvmem-cells = <&fec_mac_address>;
1087 nvmem-cell-names = "mac-address";
1088 fsl,stop-mode = <&gpr 0x10 3>;
1095 compatible = "fsl,aips-bus", "simple-bus";
1097 #address-cells = <1>;
1098 #size-cells = <1>;
1101 csi: csi@32e20000 { label
1102 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1106 clock-names = "mclk";
1107 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1112 remote-endpoint = <&imx8mm_mipi_csi_out>;
1117 disp_blk_ctrl: blk-ctrl@32e28000 {
1118 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1120 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1123 power-domain-names = "bus", "csi-bridge",
1124 "lcdif", "mipi-dsi",
1125 "mipi-csi";
1136 clock-names = "csi-bridge-axi","csi-bridge-apb",
1137 "csi-bridge-core", "lcdif-axi",
1138 "lcdif-apb", "lcdif-pix",
1139 "dsi-pclk", "dsi-ref",
1140 "csi-aclk", "csi-pclk";
1141 #power-domain-cells = <1>;
1144 mipi_csi: mipi-csi@32e30000 {
1145 compatible = "fsl,imx8mm-mipi-csi2";
1148 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
1150 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
1152 clock-frequency = <333000000>;
1157 clock-names = "pclk", "wrap", "phy", "axi";
1158 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1173 remote-endpoint = <&csi_in>;
1180 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1184 clock-names = "usb1_ctrl_root_clk";
1185 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1186 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1189 power-domains = <&pgc_hsiomix>;
1194 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1195 #index-cells = <1>;
1200 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1204 clock-names = "usb1_ctrl_root_clk";
1205 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1206 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1209 power-domains = <&pgc_hsiomix>;
1214 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1215 #index-cells = <1>;
1219 pcie_phy: pcie-phy@32f00000 {
1220 compatible = "fsl,imx8mm-pcie-phy";
1223 clock-names = "ref";
1224 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1225 assigned-clock-rates = <100000000>;
1226 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1228 reset-names = "pciephy";
1229 #phy-cells = <0>;
1234 dma_apbh: dma-controller@33000000 {
1235 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1241 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1242 #dma-cells = <1>;
1243 dma-channels = <4>;
1247 gpmi: nand-controller@33002000 {
1248 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1252 reg-names = "gpmi-nand", "bch";
1254 interrupt-names = "bch";
1257 clock-names = "gpmi_io", "gpmi_bch_apb";
1259 dma-names = "rx-tx";
1264 compatible = "fsl,imx8mm-pcie";
1266 reg-names = "dbi", "config";
1267 #address-cells = <3>;
1268 #size-cells = <2>;
1270 bus-range = <0x00 0xff>;
1272 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1273 num-lanes = <1>;
1274 num-viewport = <4>;
1276 interrupt-names = "msi";
1277 #interrupt-cells = <1>;
1278 interrupt-map-mask = <0 0 0 0x7>;
1279 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1283 fsl,max-link-speed = <2>;
1284 linux,pci-domain = <0>;
1285 power-domains = <&pgc_pcie>;
1288 reset-names = "apps", "turnoff";
1290 phy-names = "pcie-phy";
1302 clock-names = "reg", "bus", "core", "shader";
1303 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1305 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1306 assigned-clock-rates = <0>, <1000000000>;
1307 power-domains = <&pgc_gpu>;
1317 clock-names = "reg", "bus", "core";
1318 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1320 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1321 assigned-clock-rates = <0>, <1000000000>;
1322 power-domains = <&pgc_gpu>;
1325 vpu_g1: video-codec@38300000 {
1326 compatible = "nxp,imx8mm-vpu-g1";
1330 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1333 vpu_g2: video-codec@38310000 {
1334 compatible = "nxp,imx8mq-vpu-g2";
1338 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1341 vpu_blk_ctrl: blk-ctrl@38330000 {
1342 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1344 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1346 power-domain-names = "bus", "g1", "g2", "h1";
1350 clock-names = "g1", "g2", "h1";
1351 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1353 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1355 assigned-clock-rates = <600000000>,
1357 #power-domain-cells = <1>;
1360 gic: interrupt-controller@38800000 {
1361 compatible = "arm,gic-v3";
1364 #interrupt-cells = <3>;
1365 interrupt-controller;
1369 ddrc: memory-controller@3d400000 {
1370 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1372 clock-names = "core", "pll", "alt", "apb";
1379 ddr-pmu@3d800000 {
1380 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";