Lines Matching +full:0 +full:x33000000
46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
123 reg = <0x3>;
127 i-cache-size = <0x8000>;
130 d-cache-size = <0x8000>;
142 cache-size = <0x80000>;
155 opp-supported-hw = <0xe>, <0x7>;
163 opp-supported-hw = <0xc>, <0x7>;
171 opp-supported-hw = <0x8>, <0x3>;
179 #clock-cells = <0>;
186 #clock-cells = <0>;
193 #clock-cells = <0>;
200 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
273 #phy-cells = <0>;
283 #phy-cells = <0>;
292 soc: soc@0 {
296 ranges = <0x0 0x0 0x0 0x3e000000>;
297 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
303 reg = <0x30000000 0x400000>;
306 ranges = <0x30000000 0x30000000 0x400000>;
312 reg = <0x30000000 0x100000>;
316 #sound-dai-cells = <0>;
318 reg = <0x30010000 0x10000>;
324 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
330 #sound-dai-cells = <0>;
332 reg = <0x30020000 0x10000>;
338 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
344 #sound-dai-cells = <0>;
346 reg = <0x30030000 0x10000>;
352 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
358 #sound-dai-cells = <0>;
360 reg = <0x30050000 0x10000>;
366 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
372 #sound-dai-cells = <0>;
374 reg = <0x30060000 0x10000>;
380 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
387 reg = <0x30080000 0x10000>;
399 dmas = <&sdma2 24 25 0x80000000>;
406 reg = <0x30090000 0x10000>;
423 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
431 reg = <0x30200000 0x10000>;
439 gpio-ranges = <&iomuxc 0 10 30>;
444 reg = <0x30210000 0x10000>;
452 gpio-ranges = <&iomuxc 0 40 21>;
457 reg = <0x30220000 0x10000>;
465 gpio-ranges = <&iomuxc 0 61 26>;
470 reg = <0x30230000 0x10000>;
478 gpio-ranges = <&iomuxc 0 87 32>;
483 reg = <0x30240000 0x10000>;
491 gpio-ranges = <&iomuxc 0 119 30>;
496 reg = <0x30260000 0x10000>;
498 #thermal-sensor-cells = <0>;
503 reg = <0x30280000 0x10000>;
511 reg = <0x30290000 0x10000>;
519 reg = <0x302a0000 0x10000>;
527 reg = <0x302c0000 0x10000>;
538 reg = <0x302b0000 0x10000>;
549 reg = <0x30330000 0x10000>;
554 reg = <0x30340000 0x10000>;
559 reg = <0x30350000 0x10000>;
566 reg = <0x4 0x8>;
570 reg = <0x10 4>;
574 reg = <0x90 6>;
580 reg = <0x30360000 0x10000>;
584 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
585 reg = <0x30370000 0x10000>;
588 compatible = "fsl,sec-v4.0-mon-rtc-lp";
590 offset = <0x34>;
598 compatible = "fsl,sec-v4.0-pwrkey";
616 reg = <0x30380000 0x10000>;
634 assigned-clock-rates = <0>, <0>, <0>,
644 reg = <0x30390000 0x10000>;
651 reg = <0x303a0000 0x10000>;
659 #size-cells = <0>;
661 pgc_hsiomix: power-domain@0 {
662 #power-domain-cells = <0>;
670 #power-domain-cells = <0>;
677 #power-domain-cells = <0>;
682 #power-domain-cells = <0>;
687 #power-domain-cells = <0>;
699 #power-domain-cells = <0>;
710 #power-domain-cells = <0>;
718 #power-domain-cells = <0>;
723 #power-domain-cells = <0>;
728 #power-domain-cells = <0>;
733 #power-domain-cells = <0>;
745 #power-domain-cells = <0>;
754 reg = <0x30400000 0x400000>;
757 ranges = <0x30400000 0x30400000 0x400000>;
761 reg = <0x30660000 0x10000>;
772 reg = <0x30670000 0x10000>;
783 reg = <0x30680000 0x10000>;
794 reg = <0x30690000 0x10000>;
805 reg = <0x306a0000 0x20000>;
814 reg = <0x30800000 0x400000>;
817 ranges = <0x30800000 0x30800000 0x400000>,
818 <0x8000000 0x8000000 0x10000000>;
824 reg = <0x30800000 0x100000>;
830 #size-cells = <0>;
831 reg = <0x30820000 0x10000>;
836 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
844 #size-cells = <0>;
845 reg = <0x30830000 0x10000>;
858 #size-cells = <0>;
859 reg = <0x30840000 0x10000>;
871 reg = <0x30860000 0x10000>;
876 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
883 reg = <0x30880000 0x10000>;
888 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
895 reg = <0x30890000 0x10000>;
905 compatible = "fsl,sec-v4.0";
908 reg = <0x30900000 0x40000>;
909 ranges = <0 0x30900000 0x40000>;
916 compatible = "fsl,sec-v4.0-job-ring";
917 reg = <0x1000 0x1000>;
923 compatible = "fsl,sec-v4.0-job-ring";
924 reg = <0x2000 0x1000>;
929 compatible = "fsl,sec-v4.0-job-ring";
930 reg = <0x3000 0x1000>;
938 #size-cells = <0>;
939 reg = <0x30a20000 0x10000>;
948 #size-cells = <0>;
949 reg = <0x30a30000 0x10000>;
957 #size-cells = <0>;
959 reg = <0x30a40000 0x10000>;
968 #size-cells = <0>;
969 reg = <0x30a50000 0x10000>;
977 reg = <0x30a60000 0x10000>;
982 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
989 reg = <0x30aa0000 0x10000>;
997 reg = <0x30b40000 0x10000>;
1011 reg = <0x30b50000 0x10000>;
1025 reg = <0x30b60000 0x10000>;
1039 #size-cells = <0>;
1041 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1052 reg = <0x30bd0000 0x10000>;
1063 reg = <0x30be0000 0x10000>;
1083 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1088 fsl,stop-mode = <&gpr 0x10 3>;
1096 reg = <0x32c00000 0x400000>;
1099 ranges = <0x32c00000 0x32c00000 0x400000>;
1103 reg = <0x32e20000 0x1000>;
1119 reg = <0x32e28000 0x100>;
1146 reg = <0x32e30000 0x1000>;
1163 #size-cells = <0>;
1165 port@0 {
1166 reg = <0>;
1181 reg = <0x32e40000 0x200>;
1188 fsl,usbmisc = <&usbmisc1 0>;
1196 reg = <0x32e40200 0x200>;
1201 reg = <0x32e50000 0x200>;
1208 fsl,usbmisc = <&usbmisc2 0>;
1216 reg = <0x32e50200 0x200>;
1221 reg = <0x32f00000 0x10000>;
1229 #phy-cells = <0>;
1236 reg = <0x33000000 0x2000>;
1250 #size-cells = <0>;
1251 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1258 dmas = <&dma_apbh 0>;
1265 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1270 bus-range = <0x00 0xff>;
1271 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1272 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1278 interrupt-map-mask = <0 0 0 0x7>;
1279 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1280 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1281 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1282 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1284 linux,pci-domain = <0>;
1296 reg = <0x38000000 0x8000>;
1306 assigned-clock-rates = <0>, <1000000000>;
1312 reg = <0x38008000 0x8000>;
1321 assigned-clock-rates = <0>, <1000000000>;
1327 reg = <0x38300000 0x10000>;
1335 reg = <0x38310000 0x10000>;
1343 reg = <0x38330000 0x100>;
1362 reg = <0x38800000 0x10000>, /* GIC Dist */
1363 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1371 reg = <0x3d400000 0x400000>;
1381 reg = <0x3d800000 0x400000>;