Lines Matching +full:clk +full:- +full:pins

1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include "imx8mm-phycore-som.dtsi"
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
16 compatible = "phytec,imx8mm-phyboard-polis-rdk",
17 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
20 stdout-path = &uart3;
23 bt_osc_32k: bt-lp-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
26 clock-output-names = "bt_osc_32k";
27 #clock-cells = <0>;
30 can_osc_40m: can-clock {
31 compatible = "fixed-clock";
32 clock-frequency = <40000000>;
33 clock-output-names = "can_osc_40m";
34 #clock-cells = <0>;
38 compatible = "gpio-fan";
40 gpio-fan,speed-map = <0 0
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_fan>;
44 #cooling-cells = <2>;
48 compatible = "gpio-leds";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_leds>;
52 led-0 {
56 linux,default-trigger = "mmc2";
59 led-1 {
63 linux,default-trigger = "mmc1";
66 led-2 {
70 linux,default-trigger = "heartbeat";
74 usdhc1_pwrseq: pwr-seq {
75 compatible = "mmc-pwrseq-simple";
76 post-power-on-delay-ms = <100>;
77 power-off-delay-us = <60>;
78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
81 reg_can_en: regulator-can-en {
82 compatible = "regulator-fixed";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_can_en>;
86 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <3300000>;
88 regulator-name = "CAN_EN";
89 startup-delay-us = <20>;
92 reg_usb_otg1_vbus: regulator-usb-otg1 {
93 compatible = "regulator-fixed";
95 enable-active-high;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
98 regulator-name = "usb_otg1_vbus";
99 regulator-max-microvolt = <5000000>;
100 regulator-min-microvolt = <5000000>;
103 reg_usdhc2_vmmc: regulator-usdhc2 {
104 compatible = "regulator-fixed";
106 enable-active-high;
107 off-on-delay-us = <20000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
110 regulator-max-microvolt = <3300000>;
111 regulator-min-microvolt = <3300000>;
112 regulator-name = "VSD_3V3";
115 reg_vcc_3v3: regulator-vcc-3v3 {
116 compatible = "regulator-fixed";
117 regulator-max-microvolt = <3300000>;
118 regulator-min-microvolt = <3300000>;
119 regulator-name = "VCC_3V3";
123 /* SPI - CAN MCP251XFD */
125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_ecspi1>;
133 interrupt-parent = <&gpio1>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can_int>;
138 spi-max-frequency = <20000000>;
139 xceiver-supply = <&reg_can_en>;
144 gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
151 gpio-line-names = "", "", "", "",
159 gpio-line-names = "", "", "", "",
166 gpio-line-names = "", "", "", "",
173 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
174 <&clk IMX8MM_CLK_PCIE1_CTRL>;
175 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
176 <&clk IMX8MM_SYS_PLL2_250M>;
177 assigned-clock-rates = <10000000>, <250000000>;
178 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
179 <&clk IMX8MM_CLK_PCIE1_PHY>;
180 clock-names = "pcie", "pcie_aux", "pcie_bus";
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_pcie>;
183 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
188 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
189 fsl,clkreq-unsupported;
190 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
191 fsl,tx-deemph-gen1 = <0x2d>;
192 fsl,tx-deemph-gen2 = <0xf>;
197 trickle-resistor-ohms = <3000>;
204 /* UART - RS232/RS485 */
206 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
207 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart1>;
210 uart-has-rtscts;
214 /* UART - Sterling-LWB Bluetooth */
216 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
217 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
218 fsl,dte-mode;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart2_bt>;
221 uart-has-rtscts;
225 compatible = "brcm,bcm43438-bt";
227 clock-names = "lpo";
228 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
229 interrupt-names = "host-wakeup";
230 interrupt-parent = <&gpio2>;
232 max-speed = <2000000>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_bt>;
235 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
236 vddio-supply = <&reg_vcc_3v3>;
240 /* UART - console */
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_uart3>;
249 adp-disable;
251 over-current-active-low;
252 samsung,picophy-pre-emp-curr-control = <3>;
253 samsung,picophy-dc-vol-level-adjust = <7>;
254 srp-disable;
255 vbus-supply = <&reg_usb_otg1_vbus>;
260 disable-over-current;
262 samsung,picophy-pre-emp-curr-control = <3>;
263 samsung,picophy-dc-vol-level-adjust = <7>;
267 /* SDIO - Sterling-LWB Wifi */
269 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
270 assigned-clock-rates = <200000000>;
271 bus-width = <4>;
272 mmc-pwrseq = <&usdhc1_pwrseq>;
273 non-removable;
274 no-1-8-v;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
277 #address-cells = <1>;
278 #size-cells = <0>;
282 compatible = "brcm,bcm4329-fmac";
287 /* SD-Card */
289 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
290 assigned-clock-rates = <200000000>;
291 bus-width = <4>;
292 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
293 disable-wp;
294 pinctrl-names = "default", "state_100mhz", "state_200mhz";
295 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
296 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
297 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
298 vmmc-supply = <&reg_usdhc2_vmmc>;
299 vqmmc-supply = <&reg_nvcc_sd2>;
305 fsl,pins = <
312 pinctrl_can_en: can-engrp {
313 fsl,pins = <
318 pinctrl_can_int: can-intgrp {
319 fsl,pins = <
325 fsl,pins = <
334 fsl,pins = <
340 fsl,pins = <
348 fsl,pins = <
356 fsl,pins = <
362 fsl,pins = <
371 fsl,pins = <
380 fsl,pins = <
387 fsl,pins = <
393 fsl,pins = <
404 fsl,pins = <
410 fsl,pins = <
421 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
422 fsl,pins = <
433 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
434 fsl,pins = <
446 fsl,pins = <