Lines Matching +full:0 +full:x1d0
20 reg = <0x0 0x40000000 0 0x80000000>;
62 pinctrl-0 = <&pinctrl_ecspi1>;
66 flash@0 {
69 reg = <0>;
76 partition@0 {
78 reg = <0x0 0x1e0000>;
83 reg = <0x1e0000 0x10000>;
88 reg = <0x1f0000 0x10000>;
97 pinctrl-0 = <&pinctrl_i2c1>;
102 reg = <0x25>;
104 pinctrl-0 = <&pinctrl_pmic>;
106 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
110 regulator-name = "+0V8_VDD_SOC (BUCK1)";
121 regulator-name = "+0V9_VDD_ARM (BUCK2)";
132 regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
172 regulator-name = "+0V8_VDD_SNVS (LDO2)";
188 regulator-name = "+0V9_VDD_PHY (LDO4)";
205 reg = <0x52>;
207 pinctrl-0 = <&pinctrl_rtc>;
215 pinctrl-0 = <&pinctrl_uart3>;
221 pinctrl-0 = <&pinctrl_usdhc1>;
233 pinctrl-0 = <&pinctrl_wdog>;
241 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
242 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
243 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
244 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
250 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
251 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
257 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
263 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
269 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
270 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
276 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
277 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
278 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
279 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
280 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
281 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
282 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
283 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
284 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
285 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
286 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
287 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
293 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
294 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
295 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
296 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
297 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
298 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
299 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
300 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
301 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
302 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
303 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
304 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
310 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
311 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
312 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
313 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
314 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
315 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
316 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
317 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
318 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
319 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
320 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
321 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
327 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6