Lines Matching +full:interrupt +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 lsio_mem_clk: clock-lsio-mem {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <200000000>;
20 clock-output-names = "lsio_mem_clk";
23 lsio_bus_clk: clock-lsio-bus {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <100000000>;
27 clock-output-names = "lsio_bus_clk";
33 gpio-controller;
34 #gpio-cells = <2>;
35 interrupt-controller;
36 #interrupt-cells = <2>;
37 power-domains = <&pd IMX_SC_R_GPIO_0>;
43 gpio-controller;
44 #gpio-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 power-domains = <&pd IMX_SC_R_GPIO_1>;
53 gpio-controller;
54 #gpio-cells = <2>;
55 interrupt-controller;
56 #interrupt-cells = <2>;
57 power-domains = <&pd IMX_SC_R_GPIO_2>;
63 gpio-controller;
64 #gpio-cells = <2>;
65 interrupt-controller;
66 #interrupt-cells = <2>;
67 power-domains = <&pd IMX_SC_R_GPIO_3>;
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 power-domains = <&pd IMX_SC_R_GPIO_4>;
83 gpio-controller;
84 #gpio-cells = <2>;
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 power-domains = <&pd IMX_SC_R_GPIO_5>;
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 power-domains = <&pd IMX_SC_R_GPIO_6>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
107 power-domains = <&pd IMX_SC_R_GPIO_7>;
113 #mbox-cells = <2>;
120 #mbox-cells = <2>;
126 #mbox-cells = <2>;
133 #mbox-cells = <2>;
140 #mbox-cells = <2>;
147 #mbox-cells = <2>;
148 power-domains = <&pd IMX_SC_R_MU_5A>;
155 #mbox-cells = <2>;
156 power-domains = <&pd IMX_SC_R_MU_6A>;
163 #mbox-cells = <2>;
164 power-domains = <&pd IMX_SC_R_MU_13A>;
168 pwm0_lpcg: clock-controller@5d400000 {
169 compatible = "fsl,imx8qxp-lpcg";
171 #clock-cells = <1>;
172 clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
173 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
174 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
176 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
177 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
180 clock-output-names = "pwm0_lpcg_ipg_clk",
185 power-domains = <&pd IMX_SC_R_PWM_0>;
188 pwm1_lpcg: clock-controller@5d410000 {
189 compatible = "fsl,imx8qxp-lpcg";
191 #clock-cells = <1>;
192 clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
193 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
194 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
196 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
197 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
200 clock-output-names = "pwm1_lpcg_ipg_clk",
205 power-domains = <&pd IMX_SC_R_PWM_1>;
208 pwm2_lpcg: clock-controller@5d420000 {
209 compatible = "fsl,imx8qxp-lpcg";
211 #clock-cells = <1>;
212 clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
213 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
214 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
216 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
217 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
220 clock-output-names = "pwm2_lpcg_ipg_clk",
225 power-domains = <&pd IMX_SC_R_PWM_2>;
228 pwm3_lpcg: clock-controller@5d430000 {
229 compatible = "fsl,imx8qxp-lpcg";
231 #clock-cells = <1>;
232 clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
233 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
234 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
236 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
237 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
240 clock-output-names = "pwm3_lpcg_ipg_clk",
245 power-domains = <&pd IMX_SC_R_PWM_3>;
248 pwm4_lpcg: clock-controller@5d440000 {
249 compatible = "fsl,imx8qxp-lpcg";
251 #clock-cells = <1>;
252 clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
253 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
254 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
256 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
257 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
260 clock-output-names = "pwm4_lpcg_ipg_clk",
265 power-domains = <&pd IMX_SC_R_PWM_4>;
268 pwm5_lpcg: clock-controller@5d450000 {
269 compatible = "fsl,imx8qxp-lpcg";
271 #clock-cells = <1>;
272 clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
273 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
274 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
276 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
277 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
280 clock-output-names = "pwm5_lpcg_ipg_clk",
285 power-domains = <&pd IMX_SC_R_PWM_5>;
288 pwm6_lpcg: clock-controller@5d460000 {
289 compatible = "fsl,imx8qxp-lpcg";
291 #clock-cells = <1>;
292 clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
293 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
294 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
296 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
297 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
300 clock-output-names = "pwm6_lpcg_ipg_clk",
305 power-domains = <&pd IMX_SC_R_PWM_6>;
308 pwm7_lpcg: clock-controller@5d470000 {
309 compatible = "fsl,imx8qxp-lpcg";
311 #clock-cells = <1>;
312 clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
313 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
314 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
316 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
317 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
320 clock-output-names = "pwm7_lpcg_ipg_clk",
325 power-domains = <&pd IMX_SC_R_PWM_7>;