Lines Matching +full:clock +full:- +full:output +full:- +full:names

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 	compatible = "simple-bus";
12 	#address-cells = <1>;
13 	#size-cells = <1>;
16 	dma_ipg_clk: clock-dma-ipg {
17 		compatible = "fixed-clock";
18 		#clock-cells = <0>;
19 		clock-frequency = <120000000>;
20 		clock-output-names = "dma_ipg_clk";
28 		clock-names = "ipg", "baud";
29 		power-domains = <&pd IMX_SC_R_UART_0>;
38 		clock-names = "ipg", "baud";
39 		power-domains = <&pd IMX_SC_R_UART_1>;
48 		clock-names = "ipg", "baud";
49 		power-domains = <&pd IMX_SC_R_UART_2>;
58 		clock-names = "ipg", "baud";
59 		power-domains = <&pd IMX_SC_R_UART_3>;
63 	uart0_lpcg: clock-controller@5a460000 {
64 		compatible = "fsl,imx8qxp-lpcg";
66 		#clock-cells = <1>;
69 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
70 		clock-output-names = "uart0_lpcg_baud_clk",
72 		power-domains = <&pd IMX_SC_R_UART_0>;
75 	uart1_lpcg: clock-controller@5a470000 {
76 		compatible = "fsl,imx8qxp-lpcg";
78 		#clock-cells = <1>;
81 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
82 		clock-output-names = "uart1_lpcg_baud_clk",
84 		power-domains = <&pd IMX_SC_R_UART_1>;
87 	uart2_lpcg: clock-controller@5a480000 {
88 		compatible = "fsl,imx8qxp-lpcg";
90 		#clock-cells = <1>;
93 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
94 		clock-output-names = "uart2_lpcg_baud_clk",
96 		power-domains = <&pd IMX_SC_R_UART_2>;
99 	uart3_lpcg: clock-controller@5a490000 {
100 		compatible = "fsl,imx8qxp-lpcg";
102 		#clock-cells = <1>;
105 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
106 		clock-output-names = "uart3_lpcg_baud_clk",
108 		power-domains = <&pd IMX_SC_R_UART_3>;
116 		clock-names = "per", "ipg";
117 		assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
118 		assigned-clock-rates = <24000000>;
119 		power-domains = <&pd IMX_SC_R_I2C_0>;
128 		clock-names = "per", "ipg";
129 		assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
130 		assigned-clock-rates = <24000000>;
131 		power-domains = <&pd IMX_SC_R_I2C_1>;
140 		clock-names = "per", "ipg";
141 		assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
142 		assigned-clock-rates = <24000000>;
143 		power-domains = <&pd IMX_SC_R_I2C_2>;
152 		clock-names = "per", "ipg";
153 		assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
154 		assigned-clock-rates = <24000000>;
155 		power-domains = <&pd IMX_SC_R_I2C_3>;
159 	i2c0_lpcg: clock-controller@5ac00000 {
160 		compatible = "fsl,imx8qxp-lpcg";
162 		#clock-cells = <1>;
165 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
166 		clock-output-names = "i2c0_lpcg_clk",
168 		power-domains = <&pd IMX_SC_R_I2C_0>;
171 	i2c1_lpcg: clock-controller@5ac10000 {
172 		compatible = "fsl,imx8qxp-lpcg";
174 		#clock-cells = <1>;
177 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
178 		clock-output-names = "i2c1_lpcg_clk",
180 		power-domains = <&pd IMX_SC_R_I2C_1>;
183 	i2c2_lpcg: clock-controller@5ac20000 {
184 		compatible = "fsl,imx8qxp-lpcg";
186 		#clock-cells = <1>;
189 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
190 		clock-output-names = "i2c2_lpcg_clk",
192 		power-domains = <&pd IMX_SC_R_I2C_2>;
195 	i2c3_lpcg: clock-controller@5ac30000 {
196 		compatible = "fsl,imx8qxp-lpcg";
198 		#clock-cells = <1>;
201 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
202 		clock-output-names = "i2c3_lpcg_clk",
204 		power-domains = <&pd IMX_SC_R_I2C_3>;