Lines Matching +full:clock +full:- +full:output +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 conn_axi_clk: clock-conn-axi {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <333333333>;
20 clock-output-names = "conn_axi_clk";
23 conn_ahb_clk: clock-conn-ahb {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <166666666>;
27 clock-output-names = "conn_ahb_clk";
30 conn_ipg_clk: clock-conn-ipg {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <83333333>;
34 clock-output-names = "conn_ipg_clk";
43 clock-names = "ipg", "ahb", "per";
44 power-domains = <&pd IMX_SC_R_SDHC_0>;
54 clock-names = "ipg", "ahb", "per";
55 power-domains = <&pd IMX_SC_R_SDHC_1>;
56 fsl,tuning-start-tap = <20>;
57 fsl,tuning-step = <2>;
67 clock-names = "ipg", "ahb", "per";
68 power-domains = <&pd IMX_SC_R_SDHC_2>;
82 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
83 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
85 assigned-clock-rates = <250000000>, <125000000>;
86 fsl,num-tx-queues = <3>;
87 fsl,num-rx-queues = <3>;
88 power-domains = <&pd IMX_SC_R_ENET_0>;
102 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
103 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
105 assigned-clock-rates = <250000000>, <125000000>;
106 fsl,num-tx-queues = <3>;
107 fsl,num-rx-queues = <3>;
108 power-domains = <&pd IMX_SC_R_ENET_1>;
113 sdhc0_lpcg: clock-controller@5b200000 {
114 compatible = "fsl,imx8qxp-lpcg";
116 #clock-cells = <1>;
119 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
121 clock-output-names = "sdhc0_lpcg_per_clk",
124 power-domains = <&pd IMX_SC_R_SDHC_0>;
127 sdhc1_lpcg: clock-controller@5b210000 {
128 compatible = "fsl,imx8qxp-lpcg";
130 #clock-cells = <1>;
133 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
135 clock-output-names = "sdhc1_lpcg_per_clk",
138 power-domains = <&pd IMX_SC_R_SDHC_1>;
141 sdhc2_lpcg: clock-controller@5b220000 {
142 compatible = "fsl,imx8qxp-lpcg";
144 #clock-cells = <1>;
147 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
149 clock-output-names = "sdhc2_lpcg_per_clk",
152 power-domains = <&pd IMX_SC_R_SDHC_2>;
155 enet0_lpcg: clock-controller@5b230000 {
156 compatible = "fsl,imx8qxp-lpcg";
158 #clock-cells = <1>;
165 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
168 clock-output-names = "enet0_lpcg_timer_clk",
174 power-domains = <&pd IMX_SC_R_ENET_0>;
177 enet1_lpcg: clock-controller@5b240000 {
178 compatible = "fsl,imx8qxp-lpcg";
180 #clock-cells = <1>;
187 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
190 clock-output-names = "enet1_lpcg_timer_clk",
196 power-domains = <&pd IMX_SC_R_ENET_1>;