Lines Matching +full:0 +full:x5000000
33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
61 interrupts = <1 9 0x4>;
66 reg = <0x0 0x6020000 0 0x20000>;
72 reg = <0x0 0x1e60000 0x0 0x4>;
78 offset = <0x0>;
79 mask = <0x2>;
252 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
265 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
269 reg = <0 0x1300000 0 0xa0000>;
276 reg = <0x0 0x1e00000 0x0 0x10000>;
282 reg = <0x0 0x1e80000 0x0 0x10000>;
290 reg = <0x0 0x1f70000 0x0 0x10000>;
294 ranges = <0x0 0x0 0x1f70000 0x10000>;
299 #address-cells = <0>;
301 reg = <0x14 4>;
303 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
304 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
305 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
306 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
307 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
308 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
309 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
310 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
311 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
312 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
313 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
314 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
315 interrupt-map-mask = <0xf 0x0>;
321 reg = <0x0 0x1f80000 0x0 0x10000>;
322 interrupts = <0 23 0x4>;
323 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
324 fsl,tmu-calibration = <0x00000000 0x00000026
325 0x00000001 0x0000002d
326 0x00000002 0x00000032
327 0x00000003 0x00000039
328 0x00000004 0x0000003f
329 0x00000005 0x00000046
330 0x00000006 0x0000004d
331 0x00000007 0x00000054
332 0x00000008 0x0000005a
333 0x00000009 0x00000061
334 0x0000000a 0x0000006a
335 0x0000000b 0x00000071
337 0x00010000 0x00000025
338 0x00010001 0x0000002c
339 0x00010002 0x00000035
340 0x00010003 0x0000003d
341 0x00010004 0x00000045
342 0x00010005 0x0000004e
343 0x00010006 0x00000057
344 0x00010007 0x00000061
345 0x00010008 0x0000006b
346 0x00010009 0x00000076
348 0x00020000 0x00000029
349 0x00020001 0x00000033
350 0x00020002 0x0000003d
351 0x00020003 0x00000049
352 0x00020004 0x00000056
353 0x00020005 0x00000061
354 0x00020006 0x0000006d
356 0x00030000 0x00000021
357 0x00030001 0x0000002a
358 0x00030002 0x0000003c
359 0x00030003 0x0000004e>;
366 reg = <0x0 0x21c0500 0x0 0x100>;
369 interrupts = <0 32 0x4>; /* Level high type */
374 reg = <0x0 0x21c0600 0x0 0x100>;
377 interrupts = <0 32 0x4>; /* Level high type */
382 reg = <0x0 0x21d0500 0x0 0x100>;
385 interrupts = <0 33 0x4>; /* Level high type */
390 reg = <0x0 0x21d0600 0x0 0x100>;
393 interrupts = <0 33 0x4>; /* Level high type */
398 reg = <0x0 0xc000000 0x0 0x1000>;
408 reg = <0x0 0xc010000 0x0 0x1000>;
418 reg = <0x0 0xc100000 0x0 0x1000>;
428 reg = <0x0 0xc110000 0x0 0x1000>;
438 reg = <0x0 0xc200000 0x0 0x1000>;
448 reg = <0x0 0xc210000 0x0 0x1000>;
458 reg = <0x0 0xc300000 0x0 0x1000>;
468 reg = <0x0 0xc310000 0x0 0x1000>;
477 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
481 ranges = <0x0 0x00 0x8000000 0x100000>;
482 reg = <0x00 0x8000000 0x0 0x100000>;
487 compatible = "fsl,sec-v5.0-job-ring",
488 "fsl,sec-v4.0-job-ring";
489 reg = <0x10000 0x10000>;
494 compatible = "fsl,sec-v5.0-job-ring",
495 "fsl,sec-v4.0-job-ring";
496 reg = <0x20000 0x10000>;
501 compatible = "fsl,sec-v5.0-job-ring",
502 "fsl,sec-v4.0-job-ring";
503 reg = <0x30000 0x10000>;
508 compatible = "fsl,sec-v5.0-job-ring",
509 "fsl,sec-v4.0-job-ring";
510 reg = <0x40000 0x10000>;
517 reg = <0x00000000 0x08340020 0 0x2>;
522 reg = <0x0 0x8b95000 0x0 0x100>;
531 reg = <0x0 0x8b96000 0x0 0x1000>;
534 #size-cells = <0>;
543 reg = <0x0 0x8b97000 0x0 0x1000>;
546 #size-cells = <0>;
555 reg = <0x0 0x8c07000 0x0 0x1000>;
558 #size-cells = <0>;
561 pcs1: ethernet-phy@0 {
562 reg = <0>;
568 reg = <0x0 0x8c0b000 0x0 0x1000>;
571 #size-cells = <0>;
574 pcs2: ethernet-phy@0 {
575 reg = <0>;
581 reg = <0x0 0x8c0f000 0x0 0x1000>;
584 #size-cells = <0>;
587 pcs3: ethernet-phy@0 {
588 reg = <0>;
594 reg = <0x0 0x8c13000 0x0 0x1000>;
597 #size-cells = <0>;
600 pcs4: ethernet-phy@0 {
601 reg = <0>;
607 reg = <0x0 0x8c17000 0x0 0x1000>;
610 #size-cells = <0>;
613 pcs5: ethernet-phy@0 {
614 reg = <0>;
620 reg = <0x0 0x8c1b000 0x0 0x1000>;
623 #size-cells = <0>;
626 pcs6: ethernet-phy@0 {
627 reg = <0>;
633 reg = <0x0 0x8c1f000 0x0 0x1000>;
636 #size-cells = <0>;
639 pcs7: ethernet-phy@0 {
640 reg = <0>;
646 reg = <0x0 0x8c23000 0x0 0x1000>;
649 #size-cells = <0>;
652 pcs8: ethernet-phy@0 {
653 reg = <0>;
659 reg = <0x0 0x8c27000 0x0 0x1000>;
662 #size-cells = <0>;
665 pcs9: ethernet-phy@0 {
666 reg = <0>;
672 reg = <0x0 0x8c2b000 0x0 0x1000>;
675 #size-cells = <0>;
678 pcs10: ethernet-phy@0 {
679 reg = <0>;
685 reg = <0x0 0x8c2f000 0x0 0x1000>;
688 #size-cells = <0>;
691 pcs11: ethernet-phy@0 {
692 reg = <0>;
698 reg = <0x0 0x8c33000 0x0 0x1000>;
701 #size-cells = <0>;
704 pcs12: ethernet-phy@0 {
705 reg = <0>;
711 reg = <0x0 0x8c37000 0x0 0x1000>;
714 #size-cells = <0>;
717 pcs13: ethernet-phy@0 {
718 reg = <0>;
724 reg = <0x0 0x8c3b000 0x0 0x1000>;
727 #size-cells = <0>;
730 pcs14: ethernet-phy@0 {
731 reg = <0>;
737 reg = <0x0 0x8c3f000 0x0 0x1000>;
740 #size-cells = <0>;
743 pcs15: ethernet-phy@0 {
744 reg = <0>;
750 reg = <0x0 0x8c43000 0x0 0x1000>;
753 #size-cells = <0>;
756 pcs16: ethernet-phy@0 {
757 reg = <0>;
763 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
764 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
766 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
772 * Region type 0x0 - MC portals
773 * Region type 0x1 - QBMAN portals
775 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
776 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
783 #size-cells = <0>;
787 reg = <0x1>;
793 reg = <0x2>;
799 reg = <0x3>;
805 reg = <0x4>;
811 reg = <0x5>;
817 reg = <0x6>;
823 reg = <0x7>;
829 reg = <0x8>;
835 reg = <0x9>;
841 reg = <0xa>;
847 reg = <0xb>;
853 reg = <0xc>;
859 reg = <0xd>;
865 reg = <0xe>;
871 reg = <0xf>;
877 reg = <0x10>;
885 reg = <0 0x5000000 0 0x800000>;
888 stream-match-mask = <0x7C00>;
890 interrupts = <0 13 4>, /* global secure fault */
891 <0 14 4>, /* combined secure interrupt */
892 <0 15 4>, /* global non-secure fault */
893 <0 16 4>, /* combined non-secure interrupt */
894 /* performance counter interrupts 0-7 */
895 <0 211 4>, <0 212 4>,
896 <0 213 4>, <0 214 4>,
897 <0 215 4>, <0 216 4>,
898 <0 217 4>, <0 218 4>,
900 <0 146 4>, <0 147 4>,
901 <0 148 4>, <0 149 4>,
902 <0 150 4>, <0 151 4>,
903 <0 152 4>, <0 153 4>,
904 <0 154 4>, <0 155 4>,
905 <0 156 4>, <0 157 4>,
906 <0 158 4>, <0 159 4>,
907 <0 160 4>, <0 161 4>,
908 <0 162 4>, <0 163 4>,
909 <0 164 4>, <0 165 4>,
910 <0 166 4>, <0 167 4>,
911 <0 168 4>, <0 169 4>,
912 <0 170 4>, <0 171 4>,
913 <0 172 4>, <0 173 4>,
914 <0 174 4>, <0 175 4>,
915 <0 176 4>, <0 177 4>,
916 <0 178 4>, <0 179 4>,
917 <0 180 4>, <0 181 4>,
918 <0 182 4>, <0 183 4>,
919 <0 184 4>, <0 185 4>,
920 <0 186 4>, <0 187 4>,
921 <0 188 4>, <0 189 4>,
922 <0 190 4>, <0 191 4>,
923 <0 192 4>, <0 193 4>,
924 <0 194 4>, <0 195 4>,
925 <0 196 4>, <0 197 4>,
926 <0 198 4>, <0 199 4>,
927 <0 200 4>, <0 201 4>,
928 <0 202 4>, <0 203 4>,
929 <0 204 4>, <0 205 4>,
930 <0 206 4>, <0 207 4>,
931 <0 208 4>, <0 209 4>;
938 #size-cells = <0>;
939 reg = <0x0 0x2100000 0x0 0x10000>;
940 interrupts = <0 26 0x4>; /* Level high type */
950 reg = <0x0 0x2140000 0x0 0x10000>;
951 interrupts = <0 28 0x4>; /* Level high type */
962 reg = <0x0 0x2300000 0x0 0x10000>;
963 interrupts = <0 36 0x4>; /* Level high type */
973 reg = <0x0 0x2310000 0x0 0x10000>;
974 interrupts = <0 36 0x4>; /* Level high type */
984 reg = <0x0 0x2320000 0x0 0x10000>;
985 interrupts = <0 37 0x4>; /* Level high type */
995 reg = <0x0 0x2330000 0x0 0x10000>;
996 interrupts = <0 37 0x4>; /* Level high type */
1008 #size-cells = <0>;
1009 reg = <0x0 0x2000000 0x0 0x10000>;
1010 interrupts = <0 34 0x4>; /* Level high type */
1020 #size-cells = <0>;
1021 reg = <0x0 0x2010000 0x0 0x10000>;
1022 interrupts = <0 34 0x4>; /* Level high type */
1032 #size-cells = <0>;
1033 reg = <0x0 0x2020000 0x0 0x10000>;
1034 interrupts = <0 35 0x4>; /* Level high type */
1044 #size-cells = <0>;
1045 reg = <0x0 0x2030000 0x0 0x10000>;
1046 interrupts = <0 35 0x4>; /* Level high type */
1054 reg = <0x0 0x2240000 0x0 0x20000>;
1055 interrupts = <0 21 0x4>; /* Level high type */
1060 ranges = <0 0 0x5 0x80000000 0x08000000
1061 2 0 0x5 0x30000000 0x00010000
1062 3 0 0x5 0x20000000 0x00010000>;
1068 #size-cells = <0>;
1069 reg = <0x0 0x20c0000 0x0 0x10000>,
1070 <0x0 0x20000000 0x0 0x10000000>;
1084 interrupts = <0 108 0x4>; /* Level high type */
1091 bus-range = <0x0 0xff>;
1094 interrupt-map-mask = <0 0 0 7>;
1095 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1096 <0000 0 0 2 &gic 0 0 0 110 4>,
1097 <0000 0 0 3 &gic 0 0 0 111 4>,
1098 <0000 0 0 4 &gic 0 0 0 112 4>;
1099 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1106 interrupts = <0 113 0x4>; /* Level high type */
1113 bus-range = <0x0 0xff>;
1116 interrupt-map-mask = <0 0 0 7>;
1117 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1118 <0000 0 0 2 &gic 0 0 0 115 4>,
1119 <0000 0 0 3 &gic 0 0 0 116 4>,
1120 <0000 0 0 4 &gic 0 0 0 117 4>;
1121 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1128 interrupts = <0 118 0x4>; /* Level high type */
1135 bus-range = <0x0 0xff>;
1138 interrupt-map-mask = <0 0 0 7>;
1139 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1140 <0000 0 0 2 &gic 0 0 0 120 4>,
1141 <0000 0 0 3 &gic 0 0 0 121 4>,
1142 <0000 0 0 4 &gic 0 0 0 122 4>;
1143 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1150 interrupts = <0 123 0x4>; /* Level high type */
1157 bus-range = <0x0 0xff>;
1160 interrupt-map-mask = <0 0 0 7>;
1161 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1162 <0000 0 0 2 &gic 0 0 0 125 4>,
1163 <0000 0 0 3 &gic 0 0 0 126 4>,
1164 <0000 0 0 4 &gic 0 0 0 127 4>;
1165 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1172 reg = <0x0 0x3200000 0x0 0x10000>;
1173 interrupts = <0 133 0x4>; /* Level high type */
1182 reg = <0x0 0x3210000 0x0 0x10000>;
1183 interrupts = <0 136 0x4>; /* Level high type */
1192 reg = <0x0 0x3100000 0x0 0x10000>;
1193 interrupts = <0 80 0x4>; /* Level high type */
1195 snps,quirk-frame-length-adjustment = <0x20>;
1203 reg = <0x0 0x3110000 0x0 0x10000>;
1204 interrupts = <0 81 0x4>; /* Level high type */
1206 snps,quirk-frame-length-adjustment = <0x20>;
1213 reg = <0x0 0x04000000 0x0 0x01000000>;
1214 interrupts = <0 12 4>;
1219 reg = <0x0 0x1e34040 0x0 0x18>;
1226 reg = <0x0 0x2800000 0x0 0x10000>;
1227 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1234 reg = <0x0 0x1080000 0x0 0x1000>;
1235 interrupts = <0 17 0x4>;
1241 reg = <0x0 0x1090000 0x0 0x1000>;
1242 interrupts = <0 18 0x4>;