Lines Matching +full:0 +full:- +full:4
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
39 /* DRAM space - 1, size : 2 GB DRAM */
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <100000000>;
46 clock-output-names = "sysclk";
49 gic: interrupt-controller@6000000 {
50 compatible = "arm,gic-v3";
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
56 #interrupt-cells = <3>;
57 #address-cells = <2>;
58 #size-cells = <2>;
60 interrupt-controller;
61 interrupts = <1 9 0x4>;
63 its: gic-its@6020000 {
64 compatible = "arm,gic-v3-its";
65 msi-controller;
66 reg = <0x0 0x6020000 0 0x20000>;
71 compatible = "fsl,ls2080a-rstcr", "syscon";
72 reg = <0x0 0x1e60000 0x0 0x4>;
76 compatible = "syscon-reboot";
78 offset = <0x0>;
79 mask = <0x2>;
82 thermal-zones {
83 ddr-controller1 {
84 polling-delay-passive = <1000>;
85 polling-delay = <5000>;
86 thermal-sensors = <&tmu 1>;
89 ddr-ctrler1-crit {
97 ddr-controller2 {
98 polling-delay-passive = <1000>;
99 polling-delay = <5000>;
100 thermal-sensors = <&tmu 2>;
103 ddr-ctrler2-crit {
111 ddr-controller3 {
112 polling-delay-passive = <1000>;
113 polling-delay = <5000>;
114 thermal-sensors = <&tmu 3>;
117 ddr-ctrler3-crit {
125 core-cluster1 {
126 polling-delay-passive = <1000>;
127 polling-delay = <5000>;
128 thermal-sensors = <&tmu 4>;
131 core_cluster1_alert: core-cluster1-alert {
137 core-cluster1-crit {
144 cooling-maps {
147 cooling-device =
154 core-cluster2 {
155 polling-delay-passive = <1000>;
156 polling-delay = <5000>;
157 thermal-sensors = <&tmu 5>;
160 core_cluster2_alert: core-cluster2-alert {
166 core-cluster2-crit {
173 cooling-maps {
176 cooling-device =
183 core-cluster3 {
184 polling-delay-passive = <1000>;
185 polling-delay = <5000>;
186 thermal-sensors = <&tmu 6>;
189 core_cluster3_alert: core-cluster3-alert {
195 core-cluster3-crit {
202 cooling-maps {
205 cooling-device =
212 core-cluster4 {
213 polling-delay-passive = <1000>;
214 polling-delay = <5000>;
215 thermal-sensors = <&tmu 7>;
218 core_cluster4_alert: core-cluster4-alert {
224 core-cluster4-crit {
231 cooling-maps {
234 cooling-device =
243 compatible = "arm,armv8-timer";
244 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
245 <1 14 4>, /* Physical Non-Secure PPI, active-low */
246 <1 11 4>, /* Virtual PPI, active-low */
247 <1 10 4>; /* Hypervisor PPI, active-low */
251 compatible = "arm,armv8-pmuv3";
252 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
256 compatible = "arm,psci-0.2";
261 compatible = "simple-bus";
262 #address-cells = <2>;
263 #size-cells = <2>;
265 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
268 compatible = "fsl,ls2080a-clockgen";
269 reg = <0 0x1300000 0 0xa0000>;
270 #clock-cells = <2>;
275 compatible = "fsl,ls2080a-dcfg", "syscon";
276 reg = <0x0 0x1e00000 0x0 0x10000>;
277 little-endian;
281 compatible = "fsl,ls1028a-sfp";
282 reg = <0x0 0x1e80000 0x0 0x10000>;
284 QORIQ_CLK_PLL_DIV(4)>;
285 clock-names = "sfp";
289 compatible = "fsl,ls2080a-isc", "syscon";
290 reg = <0x0 0x1f70000 0x0 0x10000>;
291 little-endian;
292 #address-cells = <1>;
293 #size-cells = <1>;
294 ranges = <0x0 0x0 0x1f70000 0x10000>;
296 extirq: interrupt-controller@14 {
297 compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
298 #interrupt-cells = <2>;
299 #address-cells = <0>;
300 interrupt-controller;
301 reg = <0x14 4>;
302 interrupt-map =
303 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
304 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
305 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
306 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
307 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
308 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
309 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
310 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
311 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
312 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
313 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
314 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
315 interrupt-map-mask = <0xf 0x0>;
320 compatible = "fsl,qoriq-tmu";
321 reg = <0x0 0x1f80000 0x0 0x10000>;
322 interrupts = <0 23 0x4>;
323 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
324 fsl,tmu-calibration = <0x00000000 0x00000026
325 0x00000001 0x0000002d
326 0x00000002 0x00000032
327 0x00000003 0x00000039
328 0x00000004 0x0000003f
329 0x00000005 0x00000046
330 0x00000006 0x0000004d
331 0x00000007 0x00000054
332 0x00000008 0x0000005a
333 0x00000009 0x00000061
334 0x0000000a 0x0000006a
335 0x0000000b 0x00000071
337 0x00010000 0x00000025
338 0x00010001 0x0000002c
339 0x00010002 0x00000035
340 0x00010003 0x0000003d
341 0x00010004 0x00000045
342 0x00010005 0x0000004e
343 0x00010006 0x00000057
344 0x00010007 0x00000061
345 0x00010008 0x0000006b
346 0x00010009 0x00000076
348 0x00020000 0x00000029
349 0x00020001 0x00000033
350 0x00020002 0x0000003d
351 0x00020003 0x00000049
352 0x00020004 0x00000056
353 0x00020005 0x00000061
354 0x00020006 0x0000006d
356 0x00030000 0x00000021
357 0x00030001 0x0000002a
358 0x00030002 0x0000003c
359 0x00030003 0x0000004e>;
360 little-endian;
361 #thermal-sensor-cells = <1>;
366 reg = <0x0 0x21c0500 0x0 0x100>;
368 QORIQ_CLK_PLL_DIV(4)>;
369 interrupts = <0 32 0x4>; /* Level high type */
374 reg = <0x0 0x21c0600 0x0 0x100>;
376 QORIQ_CLK_PLL_DIV(4)>;
377 interrupts = <0 32 0x4>; /* Level high type */
382 reg = <0x0 0x21d0500 0x0 0x100>;
384 QORIQ_CLK_PLL_DIV(4)>;
385 interrupts = <0 33 0x4>; /* Level high type */
390 reg = <0x0 0x21d0600 0x0 0x100>;
392 QORIQ_CLK_PLL_DIV(4)>;
393 interrupts = <0 33 0x4>; /* Level high type */
398 reg = <0x0 0xc000000 0x0 0x1000>;
400 QORIQ_CLK_PLL_DIV(4)>,
402 QORIQ_CLK_PLL_DIV(4)>;
403 clock-names = "wdog_clk", "apb_pclk";
408 reg = <0x0 0xc010000 0x0 0x1000>;
410 QORIQ_CLK_PLL_DIV(4)>,
412 QORIQ_CLK_PLL_DIV(4)>;
413 clock-names = "wdog_clk", "apb_pclk";
418 reg = <0x0 0xc100000 0x0 0x1000>;
420 QORIQ_CLK_PLL_DIV(4)>,
422 QORIQ_CLK_PLL_DIV(4)>;
423 clock-names = "wdog_clk", "apb_pclk";
428 reg = <0x0 0xc110000 0x0 0x1000>;
430 QORIQ_CLK_PLL_DIV(4)>,
432 QORIQ_CLK_PLL_DIV(4)>;
433 clock-names = "wdog_clk", "apb_pclk";
438 reg = <0x0 0xc200000 0x0 0x1000>;
440 QORIQ_CLK_PLL_DIV(4)>,
442 QORIQ_CLK_PLL_DIV(4)>;
443 clock-names = "wdog_clk", "apb_pclk";
448 reg = <0x0 0xc210000 0x0 0x1000>;
450 QORIQ_CLK_PLL_DIV(4)>,
452 QORIQ_CLK_PLL_DIV(4)>;
453 clock-names = "wdog_clk", "apb_pclk";
458 reg = <0x0 0xc300000 0x0 0x1000>;
460 QORIQ_CLK_PLL_DIV(4)>,
462 QORIQ_CLK_PLL_DIV(4)>;
463 clock-names = "wdog_clk", "apb_pclk";
468 reg = <0x0 0xc310000 0x0 0x1000>;
470 QORIQ_CLK_PLL_DIV(4)>,
472 QORIQ_CLK_PLL_DIV(4)>;
473 clock-names = "wdog_clk", "apb_pclk";
477 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
478 fsl,sec-era = <8>;
479 #address-cells = <1>;
480 #size-cells = <1>;
481 ranges = <0x0 0x00 0x8000000 0x100000>;
482 reg = <0x00 0x8000000 0x0 0x100000>;
484 dma-coherent;
487 compatible = "fsl,sec-v5.0-job-ring",
488 "fsl,sec-v4.0-job-ring";
489 reg = <0x10000 0x10000>;
494 compatible = "fsl,sec-v5.0-job-ring",
495 "fsl,sec-v4.0-job-ring";
496 reg = <0x20000 0x10000>;
501 compatible = "fsl,sec-v5.0-job-ring",
502 "fsl,sec-v4.0-job-ring";
503 reg = <0x30000 0x10000>;
508 compatible = "fsl,sec-v5.0-job-ring",
509 "fsl,sec-v4.0-job-ring";
510 reg = <0x40000 0x10000>;
516 compatible = "fsl,dpaa2-console";
517 reg = <0x00000000 0x08340020 0 0x2>;
520 ptp-timer@8b95000 {
521 compatible = "fsl,dpaa2-ptp";
522 reg = <0x0 0x8b95000 0x0 0x100>;
525 little-endian;
526 fsl,extts-fifo;
530 compatible = "fsl,fman-memac-mdio";
531 reg = <0x0 0x8b96000 0x0 0x1000>;
532 little-endian;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 clock-frequency = <2500000>;
542 compatible = "fsl,fman-memac-mdio";
543 reg = <0x0 0x8b97000 0x0 0x1000>;
544 little-endian;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 clock-frequency = <2500000>;
554 compatible = "fsl,fman-memac-mdio";
555 reg = <0x0 0x8c07000 0x0 0x1000>;
556 little-endian;
557 #address-cells = <1>;
558 #size-cells = <0>;
561 pcs1: ethernet-phy@0 {
562 reg = <0>;
567 compatible = "fsl,fman-memac-mdio";
568 reg = <0x0 0x8c0b000 0x0 0x1000>;
569 little-endian;
570 #address-cells = <1>;
571 #size-cells = <0>;
574 pcs2: ethernet-phy@0 {
575 reg = <0>;
580 compatible = "fsl,fman-memac-mdio";
581 reg = <0x0 0x8c0f000 0x0 0x1000>;
582 little-endian;
583 #address-cells = <1>;
584 #size-cells = <0>;
587 pcs3: ethernet-phy@0 {
588 reg = <0>;
593 compatible = "fsl,fman-memac-mdio";
594 reg = <0x0 0x8c13000 0x0 0x1000>;
595 little-endian;
596 #address-cells = <1>;
597 #size-cells = <0>;
600 pcs4: ethernet-phy@0 {
601 reg = <0>;
606 compatible = "fsl,fman-memac-mdio";
607 reg = <0x0 0x8c17000 0x0 0x1000>;
608 little-endian;
609 #address-cells = <1>;
610 #size-cells = <0>;
613 pcs5: ethernet-phy@0 {
614 reg = <0>;
619 compatible = "fsl,fman-memac-mdio";
620 reg = <0x0 0x8c1b000 0x0 0x1000>;
621 little-endian;
622 #address-cells = <1>;
623 #size-cells = <0>;
626 pcs6: ethernet-phy@0 {
627 reg = <0>;
632 compatible = "fsl,fman-memac-mdio";
633 reg = <0x0 0x8c1f000 0x0 0x1000>;
634 little-endian;
635 #address-cells = <1>;
636 #size-cells = <0>;
639 pcs7: ethernet-phy@0 {
640 reg = <0>;
645 compatible = "fsl,fman-memac-mdio";
646 reg = <0x0 0x8c23000 0x0 0x1000>;
647 little-endian;
648 #address-cells = <1>;
649 #size-cells = <0>;
652 pcs8: ethernet-phy@0 {
653 reg = <0>;
658 compatible = "fsl,fman-memac-mdio";
659 reg = <0x0 0x8c27000 0x0 0x1000>;
660 little-endian;
661 #address-cells = <1>;
662 #size-cells = <0>;
665 pcs9: ethernet-phy@0 {
666 reg = <0>;
671 compatible = "fsl,fman-memac-mdio";
672 reg = <0x0 0x8c2b000 0x0 0x1000>;
673 little-endian;
674 #address-cells = <1>;
675 #size-cells = <0>;
678 pcs10: ethernet-phy@0 {
679 reg = <0>;
684 compatible = "fsl,fman-memac-mdio";
685 reg = <0x0 0x8c2f000 0x0 0x1000>;
686 little-endian;
687 #address-cells = <1>;
688 #size-cells = <0>;
691 pcs11: ethernet-phy@0 {
692 reg = <0>;
697 compatible = "fsl,fman-memac-mdio";
698 reg = <0x0 0x8c33000 0x0 0x1000>;
699 little-endian;
700 #address-cells = <1>;
701 #size-cells = <0>;
704 pcs12: ethernet-phy@0 {
705 reg = <0>;
710 compatible = "fsl,fman-memac-mdio";
711 reg = <0x0 0x8c37000 0x0 0x1000>;
712 little-endian;
713 #address-cells = <1>;
714 #size-cells = <0>;
717 pcs13: ethernet-phy@0 {
718 reg = <0>;
723 compatible = "fsl,fman-memac-mdio";
724 reg = <0x0 0x8c3b000 0x0 0x1000>;
725 little-endian;
726 #address-cells = <1>;
727 #size-cells = <0>;
730 pcs14: ethernet-phy@0 {
731 reg = <0>;
736 compatible = "fsl,fman-memac-mdio";
737 reg = <0x0 0x8c3f000 0x0 0x1000>;
738 little-endian;
739 #address-cells = <1>;
740 #size-cells = <0>;
743 pcs15: ethernet-phy@0 {
744 reg = <0>;
749 compatible = "fsl,fman-memac-mdio";
750 reg = <0x0 0x8c43000 0x0 0x1000>;
751 little-endian;
752 #address-cells = <1>;
753 #size-cells = <0>;
756 pcs16: ethernet-phy@0 {
757 reg = <0>;
761 fsl_mc: fsl-mc@80c000000 {
762 compatible = "fsl,qoriq-mc";
763 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
764 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
765 msi-parent = <&its>;
766 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
767 dma-coherent;
768 #address-cells = <3>;
769 #size-cells = <1>;
772 * Region type 0x0 - MC portals
773 * Region type 0x1 - QBMAN portals
775 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
776 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
782 #address-cells = <1>;
783 #size-cells = <0>;
786 compatible = "fsl,qoriq-mc-dpmac";
787 reg = <0x1>;
788 pcs-handle = <&pcs1>;
792 compatible = "fsl,qoriq-mc-dpmac";
793 reg = <0x2>;
794 pcs-handle = <&pcs2>;
798 compatible = "fsl,qoriq-mc-dpmac";
799 reg = <0x3>;
800 pcs-handle = <&pcs3>;
803 dpmac4: ethernet@4 {
804 compatible = "fsl,qoriq-mc-dpmac";
805 reg = <0x4>;
806 pcs-handle = <&pcs4>;
810 compatible = "fsl,qoriq-mc-dpmac";
811 reg = <0x5>;
812 pcs-handle = <&pcs5>;
816 compatible = "fsl,qoriq-mc-dpmac";
817 reg = <0x6>;
818 pcs-handle = <&pcs6>;
822 compatible = "fsl,qoriq-mc-dpmac";
823 reg = <0x7>;
824 pcs-handle = <&pcs7>;
828 compatible = "fsl,qoriq-mc-dpmac";
829 reg = <0x8>;
830 pcs-handle = <&pcs8>;
834 compatible = "fsl,qoriq-mc-dpmac";
835 reg = <0x9>;
836 pcs-handle = <&pcs9>;
840 compatible = "fsl,qoriq-mc-dpmac";
841 reg = <0xa>;
842 pcs-handle = <&pcs10>;
846 compatible = "fsl,qoriq-mc-dpmac";
847 reg = <0xb>;
848 pcs-handle = <&pcs11>;
852 compatible = "fsl,qoriq-mc-dpmac";
853 reg = <0xc>;
854 pcs-handle = <&pcs12>;
858 compatible = "fsl,qoriq-mc-dpmac";
859 reg = <0xd>;
860 pcs-handle = <&pcs13>;
864 compatible = "fsl,qoriq-mc-dpmac";
865 reg = <0xe>;
866 pcs-handle = <&pcs14>;
870 compatible = "fsl,qoriq-mc-dpmac";
871 reg = <0xf>;
872 pcs-handle = <&pcs15>;
876 compatible = "fsl,qoriq-mc-dpmac";
877 reg = <0x10>;
878 pcs-handle = <&pcs16>;
884 compatible = "arm,mmu-500";
885 reg = <0 0x5000000 0 0x800000>;
886 #global-interrupts = <12>;
887 #iommu-cells = <1>;
888 stream-match-mask = <0x7C00>;
889 dma-coherent;
890 interrupts = <0 13 4>, /* global secure fault */
891 <0 14 4>, /* combined secure interrupt */
892 <0 15 4>, /* global non-secure fault */
893 <0 16 4>, /* combined non-secure interrupt */
894 /* performance counter interrupts 0-7 */
895 <0 211 4>, <0 212 4>,
896 <0 213 4>, <0 214 4>,
897 <0 215 4>, <0 216 4>,
898 <0 217 4>, <0 218 4>,
900 <0 146 4>, <0 147 4>,
901 <0 148 4>, <0 149 4>,
902 <0 150 4>, <0 151 4>,
903 <0 152 4>, <0 153 4>,
904 <0 154 4>, <0 155 4>,
905 <0 156 4>, <0 157 4>,
906 <0 158 4>, <0 159 4>,
907 <0 160 4>, <0 161 4>,
908 <0 162 4>, <0 163 4>,
909 <0 164 4>, <0 165 4>,
910 <0 166 4>, <0 167 4>,
911 <0 168 4>, <0 169 4>,
912 <0 170 4>, <0 171 4>,
913 <0 172 4>, <0 173 4>,
914 <0 174 4>, <0 175 4>,
915 <0 176 4>, <0 177 4>,
916 <0 178 4>, <0 179 4>,
917 <0 180 4>, <0 181 4>,
918 <0 182 4>, <0 183 4>,
919 <0 184 4>, <0 185 4>,
920 <0 186 4>, <0 187 4>,
921 <0 188 4>, <0 189 4>,
922 <0 190 4>, <0 191 4>,
923 <0 192 4>, <0 193 4>,
924 <0 194 4>, <0 195 4>,
925 <0 196 4>, <0 197 4>,
926 <0 198 4>, <0 199 4>,
927 <0 200 4>, <0 201 4>,
928 <0 202 4>, <0 203 4>,
929 <0 204 4>, <0 205 4>,
930 <0 206 4>, <0 207 4>,
931 <0 208 4>, <0 209 4>;
936 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
937 #address-cells = <1>;
938 #size-cells = <0>;
939 reg = <0x0 0x2100000 0x0 0x10000>;
940 interrupts = <0 26 0x4>; /* Level high type */
942 QORIQ_CLK_PLL_DIV(4)>;
943 clock-names = "dspi";
944 spi-num-chipselects = <5>;
949 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
950 reg = <0x0 0x2140000 0x0 0x10000>;
951 interrupts = <0 28 0x4>; /* Level high type */
954 voltage-ranges = <1800 1800 3300 3300>;
955 sdhci,auto-cmd12;
956 little-endian;
957 bus-width = <4>;
961 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
962 reg = <0x0 0x2300000 0x0 0x10000>;
963 interrupts = <0 36 0x4>; /* Level high type */
964 gpio-controller;
965 little-endian;
966 #gpio-cells = <2>;
967 interrupt-controller;
968 #interrupt-cells = <2>;
972 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
973 reg = <0x0 0x2310000 0x0 0x10000>;
974 interrupts = <0 36 0x4>; /* Level high type */
975 gpio-controller;
976 little-endian;
977 #gpio-cells = <2>;
978 interrupt-controller;
979 #interrupt-cells = <2>;
983 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
984 reg = <0x0 0x2320000 0x0 0x10000>;
985 interrupts = <0 37 0x4>; /* Level high type */
986 gpio-controller;
987 little-endian;
988 #gpio-cells = <2>;
989 interrupt-controller;
990 #interrupt-cells = <2>;
994 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
995 reg = <0x0 0x2330000 0x0 0x10000>;
996 interrupts = <0 37 0x4>; /* Level high type */
997 gpio-controller;
998 little-endian;
999 #gpio-cells = <2>;
1000 interrupt-controller;
1001 #interrupt-cells = <2>;
1006 compatible = "fsl,vf610-i2c";
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1009 reg = <0x0 0x2000000 0x0 0x10000>;
1010 interrupts = <0 34 0x4>; /* Level high type */
1011 clock-names = "i2c";
1013 QORIQ_CLK_PLL_DIV(4)>;
1018 compatible = "fsl,vf610-i2c";
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 reg = <0x0 0x2010000 0x0 0x10000>;
1022 interrupts = <0 34 0x4>; /* Level high type */
1023 clock-names = "i2c";
1025 QORIQ_CLK_PLL_DIV(4)>;
1030 compatible = "fsl,vf610-i2c";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033 reg = <0x0 0x2020000 0x0 0x10000>;
1034 interrupts = <0 35 0x4>; /* Level high type */
1035 clock-names = "i2c";
1037 QORIQ_CLK_PLL_DIV(4)>;
1042 compatible = "fsl,vf610-i2c";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 reg = <0x0 0x2030000 0x0 0x10000>;
1046 interrupts = <0 35 0x4>; /* Level high type */
1047 clock-names = "i2c";
1049 QORIQ_CLK_PLL_DIV(4)>;
1052 ifc: memory-controller@2240000 {
1054 reg = <0x0 0x2240000 0x0 0x20000>;
1055 interrupts = <0 21 0x4>; /* Level high type */
1056 little-endian;
1057 #address-cells = <2>;
1058 #size-cells = <1>;
1060 ranges = <0 0 0x5 0x80000000 0x08000000
1061 2 0 0x5 0x30000000 0x00010000
1062 3 0 0x5 0x20000000 0x00010000>;
1066 compatible = "fsl,ls2080a-qspi";
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1069 reg = <0x0 0x20c0000 0x0 0x10000>,
1070 <0x0 0x20000000 0x0 0x10000000>;
1071 reg-names = "QuadSPI", "QuadSPI-memory";
1074 QORIQ_CLK_PLL_DIV(4)>,
1076 QORIQ_CLK_PLL_DIV(4)>;
1077 clock-names = "qspi_en", "qspi";
1082 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1083 reg-names = "regs", "config";
1084 interrupts = <0 108 0x4>; /* Level high type */
1085 interrupt-names = "intr";
1086 #address-cells = <3>;
1087 #size-cells = <2>;
1089 dma-coherent;
1090 num-viewport = <6>;
1091 bus-range = <0x0 0xff>;
1092 msi-parent = <&its>;
1093 #interrupt-cells = <1>;
1094 interrupt-map-mask = <0 0 0 7>;
1095 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1096 <0000 0 0 2 &gic 0 0 0 110 4>,
1097 <0000 0 0 3 &gic 0 0 0 111 4>,
1098 <0000 0 0 4 &gic 0 0 0 112 4>;
1099 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1104 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1105 reg-names = "regs", "config";
1106 interrupts = <0 113 0x4>; /* Level high type */
1107 interrupt-names = "intr";
1108 #address-cells = <3>;
1109 #size-cells = <2>;
1111 dma-coherent;
1112 num-viewport = <6>;
1113 bus-range = <0x0 0xff>;
1114 msi-parent = <&its>;
1115 #interrupt-cells = <1>;
1116 interrupt-map-mask = <0 0 0 7>;
1117 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1118 <0000 0 0 2 &gic 0 0 0 115 4>,
1119 <0000 0 0 3 &gic 0 0 0 116 4>,
1120 <0000 0 0 4 &gic 0 0 0 117 4>;
1121 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1126 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1127 reg-names = "regs", "config";
1128 interrupts = <0 118 0x4>; /* Level high type */
1129 interrupt-names = "intr";
1130 #address-cells = <3>;
1131 #size-cells = <2>;
1133 dma-coherent;
1134 num-viewport = <256>;
1135 bus-range = <0x0 0xff>;
1136 msi-parent = <&its>;
1137 #interrupt-cells = <1>;
1138 interrupt-map-mask = <0 0 0 7>;
1139 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1140 <0000 0 0 2 &gic 0 0 0 120 4>,
1141 <0000 0 0 3 &gic 0 0 0 121 4>,
1142 <0000 0 0 4 &gic 0 0 0 122 4>;
1143 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1148 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1149 reg-names = "regs", "config";
1150 interrupts = <0 123 0x4>; /* Level high type */
1151 interrupt-names = "intr";
1152 #address-cells = <3>;
1153 #size-cells = <2>;
1155 dma-coherent;
1156 num-viewport = <6>;
1157 bus-range = <0x0 0xff>;
1158 msi-parent = <&its>;
1159 #interrupt-cells = <1>;
1160 interrupt-map-mask = <0 0 0 7>;
1161 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1162 <0000 0 0 2 &gic 0 0 0 125 4>,
1163 <0000 0 0 3 &gic 0 0 0 126 4>,
1164 <0000 0 0 4 &gic 0 0 0 127 4>;
1165 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1171 compatible = "fsl,ls2080a-ahci";
1172 reg = <0x0 0x3200000 0x0 0x10000>;
1173 interrupts = <0 133 0x4>; /* Level high type */
1175 QORIQ_CLK_PLL_DIV(4)>;
1176 dma-coherent;
1181 compatible = "fsl,ls2080a-ahci";
1182 reg = <0x0 0x3210000 0x0 0x10000>;
1183 interrupts = <0 136 0x4>; /* Level high type */
1185 QORIQ_CLK_PLL_DIV(4)>;
1186 dma-coherent;
1192 reg = <0x0 0x3100000 0x0 0x10000>;
1193 interrupts = <0 80 0x4>; /* Level high type */
1195 snps,quirk-frame-length-adjustment = <0x20>;
1197 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1203 reg = <0x0 0x3110000 0x0 0x10000>;
1204 interrupts = <0 81 0x4>; /* Level high type */
1206 snps,quirk-frame-length-adjustment = <0x20>;
1208 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1212 compatible = "arm,ccn-504";
1213 reg = <0x0 0x04000000 0x0 0x01000000>;
1214 interrupts = <0 12 4>;
1217 rcpm: power-controller@1e34040 {
1218 compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1219 reg = <0x0 0x1e34040 0x0 0x18>;
1220 #fsl,rcpm-wakeup-cells = <6>;
1221 little-endian;
1225 compatible = "fsl,ls208xa-ftm-alarm";
1226 reg = <0x0 0x2800000 0x0 0x10000>;
1227 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1232 ddr1: memory-controller@1080000 {
1233 compatible = "fsl,qoriq-memory-controller";
1234 reg = <0x0 0x1080000 0x0 0x1000>;
1235 interrupts = <0 17 0x4>;
1236 little-endian;
1239 ddr2: memory-controller@1090000 {
1240 compatible = "fsl,qoriq-memory-controller";
1241 reg = <0x0 0x1090000 0x0 0x1000>;
1242 interrupts = <0 18 0x4>;
1243 little-endian;
1248 compatible = "linaro,optee-tz";