Lines Matching +full:next +full:- +full:level +full:- +full:cache

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
18 		compatible = "arm,cortex-a72";
21 		cpu-idle-states = <&CPU_PW20>;
22 		next-level-cache = <&cluster0_l2>;
23 		#cooling-cells = <2>;
28 		compatible = "arm,cortex-a72";
31 		cpu-idle-states = <&CPU_PW20>;
32 		next-level-cache = <&cluster0_l2>;
33 		#cooling-cells = <2>;
38 		compatible = "arm,cortex-a72";
41 		cpu-idle-states = <&CPU_PW20>;
42 		next-level-cache = <&cluster1_l2>;
43 		#cooling-cells = <2>;
48 		compatible = "arm,cortex-a72";
51 		cpu-idle-states = <&CPU_PW20>;
52 		next-level-cache = <&cluster1_l2>;
53 		#cooling-cells = <2>;
58 		compatible = "arm,cortex-a72";
61 		next-level-cache = <&cluster2_l2>;
62 		cpu-idle-states = <&CPU_PW20>;
63 		#cooling-cells = <2>;
68 		compatible = "arm,cortex-a72";
71 		cpu-idle-states = <&CPU_PW20>;
72 		next-level-cache = <&cluster2_l2>;
73 		#cooling-cells = <2>;
78 		compatible = "arm,cortex-a72";
81 		cpu-idle-states = <&CPU_PW20>;
82 		next-level-cache = <&cluster3_l2>;
83 		#cooling-cells = <2>;
88 		compatible = "arm,cortex-a72";
91 		cpu-idle-states = <&CPU_PW20>;
92 		next-level-cache = <&cluster3_l2>;
93 		#cooling-cells = <2>;
96 	cluster0_l2: l2-cache0 {
97 		compatible = "cache";
100 	cluster1_l2: l2-cache1 {
101 		compatible = "cache";
104 	cluster2_l2: l2-cache2 {
105 		compatible = "cache";
108 	cluster3_l2: l2-cache3 {
109 		compatible = "cache";
112 	CPU_PW20: cpu-pw20 {
113 		compatible = "arm,idle-state";
114 		idle-state-name = "PW20";
115 		arm,psci-suspend-param = <0x0>;
116 		entry-latency-us = <2000>;
117 		exit-latency-us = <2000>;
118 		min-residency-us = <6000>;
123 	compatible = "fsl,ls2088a-pcie";
132 	compatible = "fsl,ls2088a-pcie";
141 	compatible = "fsl,ls2088a-pcie";
150 	compatible = "fsl,ls2088a-pcie";