Lines Matching +full:0 +full:x5000000
27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
69 reg = <0x100>;
78 reg = <0x101>;
87 reg = <0x102>;
96 reg = <0x103>;
105 arm,psci-suspend-param = <0x0>;
116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
129 reg = <0x0 0x6020000 0 0x20000>;
137 thermal-sensors = <&tmu 0>;
204 #clock-cells = <0>;
212 offset = <0x0>;
213 mask = <0x02>;
221 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
225 reg = <0 0x1300000 0 0xa0000>;
232 reg = <0x0 0x1e00000 0x0 0x10000>;
238 reg = <0x0 0x1e60000 0x0 0x10000>;
243 reg = <0x0 0x1f70000 0x0 0x10000>;
247 ranges = <0x0 0x0 0x1f70000 0x10000>;
252 #address-cells = <0>;
254 reg = <0x14 4>;
256 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
257 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
258 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
259 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
260 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
261 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
262 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
263 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
264 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
265 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
266 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
267 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-map-mask = <0xf 0x0>;
274 reg = <0x0 0x1e80000 0x0 0x10000>;
282 reg = <0x0 0x1f80000 0x0 0x10000>;
283 interrupts = <0 23 0x4>;
284 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
287 <0x00000000 0x00000023
288 0x00000001 0x0000002a
289 0x00000002 0x00000030
290 0x00000003 0x00000037
291 0x00000004 0x0000003d
292 0x00000005 0x00000044
293 0x00000006 0x0000004a
294 0x00000007 0x00000051
295 0x00000008 0x00000057
296 0x00000009 0x0000005e
297 0x0000000a 0x00000064
298 0x0000000b 0x0000006b
300 0x00010000 0x00000022
301 0x00010001 0x0000002a
302 0x00010002 0x00000032
303 0x00010003 0x0000003a
304 0x00010004 0x00000042
305 0x00010005 0x0000004a
306 0x00010006 0x00000052
307 0x00010007 0x0000005a
308 0x00010008 0x00000062
309 0x00010009 0x0000006a
311 0x00020000 0x00000021
312 0x00020001 0x0000002b
313 0x00020002 0x00000035
314 0x00020003 0x00000040
315 0x00020004 0x0000004a
316 0x00020005 0x00000054
317 0x00020006 0x0000005e
319 0x00030000 0x00000010
320 0x00030001 0x0000001c
321 0x00030002 0x00000027
322 0x00030003 0x00000032
323 0x00030004 0x0000003e
324 0x00030005 0x00000049
325 0x00030006 0x00000054
326 0x00030007 0x00000060>;
333 "fsl,ls1021a-v1.0-dspi";
335 #size-cells = <0>;
336 reg = <0x0 0x2100000 0x0 0x10000>;
347 reg = <0x0 0x21c0500 0x0 0x100>;
350 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
356 reg = <0x0 0x21c0600 0x0 0x100>;
359 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
365 reg = <0x0 0x2300000 0x0 0x10000>;
366 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
376 reg = <0x0 0x2310000 0x0 0x10000>;
377 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
387 reg = <0x0 0x2320000 0x0 0x10000>;
388 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
398 reg = <0x0 0x2330000 0x0 0x10000>;
399 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
409 reg = <0x0 0x2240000 0x0 0x20000>;
410 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
420 #size-cells = <0>;
421 reg = <0x0 0x2000000 0x0 0x10000>;
422 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
431 #size-cells = <0>;
432 reg = <0x0 0x2010000 0x0 0x10000>;
433 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
442 #size-cells = <0>;
443 reg = <0x0 0x2020000 0x0 0x10000>;
444 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
453 #size-cells = <0>;
454 reg = <0x0 0x2030000 0x0 0x10000>;
455 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
464 #size-cells = <0>;
465 reg = <0x0 0x20c0000 0x0 0x10000>,
466 <0x0 0x20000000 0x0 0x10000000>;
479 reg = <0x0 0x2140000 0x0 0x10000>;
480 interrupts = <0 28 0x4>; /* Level high type */
481 clock-frequency = <0>;
492 reg = <0x0 0x3100000 0x0 0x10000>;
493 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
495 snps,quirk-frame-length-adjustment = <0x20>;
503 reg = <0x0 0x3110000 0x0 0x10000>;
504 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
506 snps,quirk-frame-length-adjustment = <0x20>;
514 reg = <0x0 0x3200000 0x0 0x10000>,
515 <0x7 0x100520 0x0 0x4>;
517 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
525 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
529 ranges = <0x0 0x00 0x8000000 0x100000>;
530 reg = <0x00 0x8000000 0x0 0x100000>;
535 compatible = "fsl,sec-v5.0-job-ring",
536 "fsl,sec-v4.0-job-ring";
537 reg = <0x10000 0x10000>;
542 compatible = "fsl,sec-v5.0-job-ring",
543 "fsl,sec-v4.0-job-ring";
544 reg = <0x20000 0x10000>;
549 compatible = "fsl,sec-v5.0-job-ring",
550 "fsl,sec-v4.0-job-ring";
551 reg = <0x30000 0x10000>;
556 compatible = "fsl,sec-v5.0-job-ring",
557 "fsl,sec-v4.0-job-ring";
558 reg = <0x40000 0x10000>;
565 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
566 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
568 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
575 bus-range = <0x0 0xff>;
576 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
577 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
580 interrupt-map-mask = <0 0 0 7>;
581 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
582 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
583 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
584 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
585 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
591 reg = <0x00 0x03400000 0x0 0x00100000>,
592 <0x20 0x00000000 0x8 0x00000000>;
602 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
603 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
605 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
612 bus-range = <0x0 0xff>;
613 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
614 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
617 interrupt-map-mask = <0 0 0 7>;
618 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
619 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
620 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
621 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
622 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
628 reg = <0x00 0x03500000 0x0 0x00100000>,
629 <0x28 0x00000000 0x8 0x00000000>;
638 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
639 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
641 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
648 bus-range = <0x0 0xff>;
649 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
650 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
653 interrupt-map-mask = <0 0 0 7>;
654 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
655 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
656 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
657 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
658 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
664 reg = <0x00 0x03600000 0x0 0x00100000>,
665 <0x30 0x00000000 0x8 0x00000000>;
674 reg = <0 0x5000000 0 0x800000>;
676 stream-match-mask = <0x7C00>;
686 // performance counter interrupts 0-7
764 reg = <0x00000000 0x08340020 0 0x2>;
769 reg = <0x0 0x8b95000 0x0 0x100>;
778 reg = <0x0 0x8b96000 0x0 0x1000>;
781 #size-cells = <0>;
790 reg = <0x0 0x8b97000 0x0 0x1000>;
793 #size-cells = <0>;
802 reg = <0x0 0x8c07000 0x0 0x1000>;
805 #size-cells = <0>;
808 pcs1: ethernet-phy@0 {
809 reg = <0>;
815 reg = <0x0 0x8c0b000 0x0 0x1000>;
818 #size-cells = <0>;
821 pcs2: ethernet-phy@0 {
822 reg = <0>;
828 reg = <0x0 0x8c0f000 0x0 0x1000>;
831 #size-cells = <0>;
834 pcs3_0: ethernet-phy@0 {
835 reg = <0>;
853 reg = <0x0 0x8c1f000 0x0 0x1000>;
856 #size-cells = <0>;
859 pcs7_0: ethernet-phy@0 {
860 reg = <0>;
878 reg = <0x0 0xc000000 0x0 0x1000>;
888 reg = <0x0 0xc010000 0x0 0x1000>;
898 reg = <0x0 0xc020000 0x0 0x1000>;
908 reg = <0x0 0xc030000 0x0 0x1000>;
918 reg = <0x0 0xc100000 0x0 0x1000>;
928 reg = <0x0 0xc110000 0x0 0x1000>;
938 reg = <0x0 0xc120000 0x0 0x1000>;
948 reg = <0x0 0xc130000 0x0 0x1000>;
958 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
959 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
961 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
967 * Region type 0x0 - MC portals
968 * Region type 0x1 - QBMAN portals
970 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
971 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
975 #size-cells = <0>;
1024 reg = <0xa>;
1031 reg = <0x0 0x1e34040 0x0 0x18>;
1038 reg = <0x0 0x2800000 0x0 0x10000>;
1039 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;