Lines Matching +full:0 +full:x10000
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
95 arm,psci-suspend-param = <0x0>;
105 reg = <0x0 0x80000000 0x0 0x0>;
110 #clock-cells = <0>;
118 offset = <0xb0>;
119 mask = <0x02>;
126 thermal-sensors = <&tmu 0>;
237 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
239 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
241 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
243 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
263 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
264 <0x0 0x1420000 0 0x20000>, /* GICC */
265 <0x0 0x1440000 0 0x20000>, /* GICH */
266 <0x0 0x1460000 0 0x20000>; /* GICV */
267 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
276 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
281 reg = <0x0 0x1080000 0x0 0x1000>;
288 reg = <0x0 0x1530000 0x0 0x10000>;
296 #size-cells = <0>;
297 reg = <0x0 0x1550000 0x0 0x10000>,
298 <0x0 0x40000000 0x0 0x10000000>;
311 reg = <0x0 0x1560000 0x0 0x10000>;
322 reg = <0x0 0x1570000 0x0 0x10000>;
326 ranges = <0x0 0x0 0x1570000 0x10000>;
331 #address-cells = <0>;
333 reg = <0x1ac 4>;
335 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
336 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
337 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
338 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
339 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
340 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
341 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
342 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
343 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
344 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
345 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
346 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-map-mask = <0xf 0x0>;
352 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
353 "fsl,sec-v4.0";
357 ranges = <0x0 0x00 0x1700000 0x100000>;
358 reg = <0x00 0x1700000 0x0 0x100000>;
363 "fsl,sec-v5.0-job-ring",
364 "fsl,sec-v4.0-job-ring";
365 reg = <0x10000 0x10000>;
371 "fsl,sec-v5.0-job-ring",
372 "fsl,sec-v4.0-job-ring";
373 reg = <0x20000 0x10000>;
379 "fsl,sec-v5.0-job-ring",
380 "fsl,sec-v4.0-job-ring";
381 reg = <0x30000 0x10000>;
387 "fsl,sec-v5.0-job-ring",
388 "fsl,sec-v4.0-job-ring";
389 reg = <0x40000 0x10000>;
396 reg = <0x0 0x1880000 0x0 0x10000>;
404 reg = <0x0 0x1890000 0x0 0x10000>;
411 ranges = <0x0 0x5 0x00000000 0x8000000>;
415 ranges = <0x0 0x5 0x08000000 0x8000000>;
420 reg = <0x0 0x1e80000 0x0 0x10000>;
428 reg = <0x0 0x1ee0000 0x0 0x1000>;
434 reg = <0x0 0x1ee1000 0x0 0x1000>;
441 reg = <0x0 0x1f00000 0x0 0x10000>;
442 interrupts = <0 33 0x4>;
443 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
446 <0x00000000 0x00000023
447 0x00000001 0x00000029
448 0x00000002 0x0000002f
449 0x00000003 0x00000036
450 0x00000004 0x0000003c
451 0x00000005 0x00000042
452 0x00000006 0x00000049
453 0x00000007 0x0000004f
454 0x00000008 0x00000055
455 0x00000009 0x0000005c
456 0x0000000a 0x00000062
457 0x0000000b 0x00000068
459 0x00010000 0x00000022
460 0x00010001 0x0000002a
461 0x00010002 0x00000032
462 0x00010003 0x0000003a
463 0x00010004 0x00000042
464 0x00010005 0x0000004a
465 0x00010006 0x00000052
466 0x00010007 0x0000005a
467 0x00010008 0x00000062
468 0x00010009 0x0000006a
470 0x00020000 0x00000021
471 0x00020001 0x0000002b
472 0x00020002 0x00000035
473 0x00020003 0x0000003e
474 0x00020004 0x00000048
475 0x00020005 0x00000052
476 0x00020006 0x0000005c
478 0x00030000 0x00000011
479 0x00030001 0x0000001a
480 0x00030002 0x00000024
481 0x00030003 0x0000002e
482 0x00030004 0x00000038
483 0x00030005 0x00000042
484 0x00030006 0x0000004c
485 0x00030007 0x00000056>;
491 compatible = "fsl,ls1021a-v1.0-dspi";
493 #size-cells = <0>;
494 reg = <0x0 0x2100000 0x0 0x10000>;
507 #size-cells = <0>;
508 reg = <0x0 0x2180000 0x0 0x10000>;
521 #size-cells = <0>;
522 reg = <0x0 0x2190000 0x0 0x10000>;
533 #size-cells = <0>;
534 reg = <0x0 0x21a0000 0x0 0x10000>;
545 #size-cells = <0>;
546 reg = <0x0 0x21b0000 0x0 0x10000>;
556 reg = <0x00 0x21c0500 0x0 0x100>;
565 reg = <0x00 0x21c0600 0x0 0x100>;
574 reg = <0x0 0x21d0500 0x0 0x100>;
583 reg = <0x0 0x21d0600 0x0 0x100>;
592 reg = <0x0 0x2300000 0x0 0x10000>;
602 reg = <0x0 0x2310000 0x0 0x10000>;
612 reg = <0x0 0x2320000 0x0 0x10000>;
622 reg = <0x0 0x2330000 0x0 0x10000>;
632 reg = <0x0 0x2950000 0x0 0x1000>;
642 reg = <0x0 0x2960000 0x0 0x1000>;
652 reg = <0x0 0x2970000 0x0 0x1000>;
662 reg = <0x0 0x2980000 0x0 0x1000>;
672 reg = <0x0 0x2990000 0x0 0x1000>;
682 reg = <0x0 0x29a0000 0x0 0x1000>;
692 reg = <0x0 0x2ad0000 0x0 0x10000>;
702 reg = <0x0 0x2c00000 0x0 0x10000>,
703 <0x0 0x2c10000 0x0 0x10000>,
704 <0x0 0x2c20000 0x0 0x10000>;
722 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
726 reg = <0x0 0x2f00000 0x0 0x10000>;
729 snps,quirk-frame-length-adjustment = <0x20>;
737 reg = <0x0 0x3000000 0x0 0x10000>;
740 snps,quirk-frame-length-adjustment = <0x20>;
748 reg = <0x0 0x3100000 0x0 0x10000>;
751 snps,quirk-frame-length-adjustment = <0x20>;
759 reg = <0x0 0x3200000 0x0 0x10000>,
760 <0x0 0x20140520 0x0 0x4>;
771 reg = <0x0 0x1580000 0x0 0x10000>;
781 reg = <0x0 0x1590000 0x0 0x10000>;
791 reg = <0x0 0x15a0000 0x0 0x10000>;
800 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
801 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
810 bus-range = <0x0 0xff>;
811 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
812 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
815 interrupt-map-mask = <0 0 0 7>;
816 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
817 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
818 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
819 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
826 reg = <0x00 0x03400000 0x0 0x00100000>,
827 <0x40 0x00000000 0x8 0x00000000>;
839 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
840 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
849 bus-range = <0x0 0xff>;
850 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
851 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
854 interrupt-map-mask = <0 0 0 7>;
855 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
856 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
857 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
858 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
865 reg = <0x00 0x03500000 0x0 0x00100000>,
866 <0x48 0x00000000 0x8 0x00000000>;
878 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
879 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
888 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
893 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
895 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
896 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
897 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
904 reg = <0x00 0x03600000 0x0 0x00100000>,
905 <0x50 0x00000000 0x8 0x00000000>;
917 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
918 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
919 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
929 block-offset = <0x10000>;
938 reg = <0x0 0x1ee2140 0x0 0x4>;
944 reg = <0x0 0x29d0000 0x0 0x10000>;
945 fsl,rcpm-wakeup = <&rcpm 0x20000>;
958 size = <0 0x1000000>;
959 alignment = <0 0x1000000>;
965 size = <0 0x800000>;
966 alignment = <0 0x800000>;
972 size = <0 0x2000000>;
973 alignment = <0 0x2000000>;