Lines Matching +full:0 +full:x10000
37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
100 arm,psci-suspend-param = <0x0>;
109 reg = <0x0 0x80000000 0 0x80000000>;
120 size = <0 0x1000000>;
121 alignment = <0 0x1000000>;
127 size = <0 0x400000>;
128 alignment = <0 0x400000>;
134 size = <0 0x2000000>;
135 alignment = <0 0x2000000>;
142 #clock-cells = <0>;
150 offset = <0xb0>;
151 mask = <0x02>;
158 thermal-sensors = <&tmu 0>;
269 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
270 <1 14 0xf08>, /* Physical Non-Secure PPI */
271 <1 11 0xf08>, /* Virtual PPI */
272 <1 10 0xf08>; /* Hypervisor PPI */
278 interrupts = <0 106 0x4>,
279 <0 107 0x4>,
280 <0 95 0x4>,
281 <0 97 0x4>;
292 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
293 <0x0 0x1402000 0 0x2000>, /* GICC */
294 <0x0 0x1404000 0 0x2000>, /* GICH */
295 <0x0 0x1406000 0 0x2000>; /* GICV */
296 interrupts = <1 9 0xf08>;
304 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
309 reg = <0x0 0x1ee1000 0x0 0x1000>;
316 reg = <0x0 0x1570000 0x0 0x10000>;
320 ranges = <0x0 0x0 0x1570000 0x10000>;
325 #address-cells = <0>;
327 reg = <0x1ac 4>;
329 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
330 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
331 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
332 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
333 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
334 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
335 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
336 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
337 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
338 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
339 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
340 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
341 interrupt-map-mask = <0xf 0x0>;
346 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
347 "fsl,sec-v4.0";
351 ranges = <0x0 0x00 0x1700000 0x100000>;
352 reg = <0x00 0x1700000 0x0 0x100000>;
353 interrupts = <0 75 0x4>;
358 "fsl,sec-v5.0-job-ring",
359 "fsl,sec-v4.0-job-ring";
360 reg = <0x10000 0x10000>;
361 interrupts = <0 71 0x4>;
366 "fsl,sec-v5.0-job-ring",
367 "fsl,sec-v4.0-job-ring";
368 reg = <0x20000 0x10000>;
369 interrupts = <0 72 0x4>;
374 "fsl,sec-v5.0-job-ring",
375 "fsl,sec-v4.0-job-ring";
376 reg = <0x30000 0x10000>;
377 interrupts = <0 73 0x4>;
382 "fsl,sec-v5.0-job-ring",
383 "fsl,sec-v4.0-job-ring";
384 reg = <0x40000 0x10000>;
385 interrupts = <0 74 0x4>;
391 reg = <0x0 0x1e80000 0x0 0x10000>;
399 reg = <0x0 0x1ee0000 0x0 0x1000>;
405 reg = <0x0 0x1530000 0x0 0x10000>;
406 interrupts = <0 43 0x4>;
412 #size-cells = <0>;
413 reg = <0x0 0x1550000 0x0 0x10000>,
414 <0x0 0x40000000 0x0 0x4000000>;
416 interrupts = <0 99 0x4>;
427 reg = <0x0 0x1560000 0x0 0x10000>;
428 interrupts = <0 62 0x4>;
429 clock-frequency = <0>;
438 reg = <0x0 0x1080000 0x0 0x1000>;
439 interrupts = <0 144 0x4>;
445 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <0 33 0x4>;
447 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
448 fsl,tmu-calibration = <0x00000000 0x00000023
449 0x00000001 0x0000002a
450 0x00000002 0x00000031
451 0x00000003 0x00000037
452 0x00000004 0x0000003e
453 0x00000005 0x00000044
454 0x00000006 0x0000004b
455 0x00000007 0x00000051
456 0x00000008 0x00000058
457 0x00000009 0x0000005e
458 0x0000000a 0x00000065
459 0x0000000b 0x0000006b
461 0x00010000 0x00000023
462 0x00010001 0x0000002b
463 0x00010002 0x00000033
464 0x00010003 0x0000003b
465 0x00010004 0x00000043
466 0x00010005 0x0000004b
467 0x00010006 0x00000054
468 0x00010007 0x0000005c
469 0x00010008 0x00000064
470 0x00010009 0x0000006c
472 0x00020000 0x00000021
473 0x00020001 0x0000002c
474 0x00020002 0x00000036
475 0x00020003 0x00000040
476 0x00020004 0x0000004b
477 0x00020005 0x00000055
478 0x00020006 0x0000005f
480 0x00030000 0x00000013
481 0x00030001 0x0000001d
482 0x00030002 0x00000028
483 0x00030003 0x00000032
484 0x00030004 0x0000003d
485 0x00030005 0x00000047
486 0x00030006 0x00000052
487 0x00030007 0x0000005c>;
493 reg = <0x0 0x1880000 0x0 0x10000>;
500 reg = <0x0 0x1890000 0x0 0x10000>;
506 ranges = <0x0 0x5 0x08000000 0x8000000>;
510 ranges = <0x0 0x5 0x00000000 0x8000000>;
514 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #size-cells = <0>;
517 reg = <0x0 0x2100000 0x0 0x10000>;
518 interrupts = <0 64 0x4>;
528 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
530 #size-cells = <0>;
531 reg = <0x0 0x2110000 0x0 0x10000>;
532 interrupts = <0 65 0x4>;
544 #size-cells = <0>;
545 reg = <0x0 0x2180000 0x0 0x10000>;
546 interrupts = <0 56 0x4>;
559 #size-cells = <0>;
560 reg = <0x0 0x2190000 0x0 0x10000>;
561 interrupts = <0 57 0x4>;
572 #size-cells = <0>;
573 reg = <0x0 0x21a0000 0x0 0x10000>;
574 interrupts = <0 58 0x4>;
585 #size-cells = <0>;
586 reg = <0x0 0x21b0000 0x0 0x10000>;
587 interrupts = <0 59 0x4>;
597 reg = <0x00 0x21c0500 0x0 0x100>;
598 interrupts = <0 54 0x4>;
605 reg = <0x00 0x21c0600 0x0 0x100>;
606 interrupts = <0 54 0x4>;
613 reg = <0x0 0x21d0500 0x0 0x100>;
614 interrupts = <0 55 0x4>;
621 reg = <0x0 0x21d0600 0x0 0x100>;
622 interrupts = <0 55 0x4>;
629 reg = <0x0 0x2300000 0x0 0x10000>;
630 interrupts = <0 66 0x4>;
639 reg = <0x0 0x2310000 0x0 0x10000>;
640 interrupts = <0 67 0x4>;
649 reg = <0x0 0x2320000 0x0 0x10000>;
650 interrupts = <0 68 0x4>;
659 reg = <0x0 0x2330000 0x0 0x10000>;
660 interrupts = <0 134 0x4>;
671 ranges = <0x0 0x0 0x2400000 0x40000>;
672 reg = <0x0 0x2400000 0x0 0x480>;
680 reg = <0x80 0x80>;
681 #address-cells = <0>;
690 #size-cells = <0>;
693 reg = <0x700 0x80>;
701 reg = <0x1000 0x800>;
706 reg = <0x2000 0x200>;
713 reg = <0x2200 0x200>;
722 ranges = <0x0 0x10000 0x6000>;
724 data-only@0 {
727 reg = <0x0 0x6000>;
734 reg = <0x0 0x2950000 0x0 0x1000>;
735 interrupts = <0 48 0x4>;
736 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
743 reg = <0x0 0x2960000 0x0 0x1000>;
744 interrupts = <0 49 0x4>;
753 reg = <0x0 0x2970000 0x0 0x1000>;
754 interrupts = <0 50 0x4>;
763 reg = <0x0 0x2980000 0x0 0x1000>;
764 interrupts = <0 51 0x4>;
773 reg = <0x0 0x2990000 0x0 0x1000>;
774 interrupts = <0 52 0x4>;
783 reg = <0x0 0x29a0000 0x0 0x1000>;
784 interrupts = <0 53 0x4>;
793 reg = <0x0 0x2ad0000 0x0 0x10000>;
794 interrupts = <0 83 0x4>;
804 reg = <0x0 0x2c00000 0x0 0x10000>,
805 <0x0 0x2c10000 0x0 0x10000>,
806 <0x0 0x2c20000 0x0 0x10000>;
807 interrupts = <0 103 0x4>,
808 <0 103 0x4>;
824 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
828 reg = <0x0 0x2f00000 0x0 0x10000>;
829 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
831 snps,quirk-frame-length-adjustment = <0x20>;
840 reg = <0x0 0x3000000 0x0 0x10000>;
841 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
843 snps,quirk-frame-length-adjustment = <0x20>;
852 reg = <0x0 0x3100000 0x0 0x10000>;
853 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
855 snps,quirk-frame-length-adjustment = <0x20>;
864 reg = <0x0 0x3200000 0x0 0x10000>,
865 <0x0 0x20140520 0x0 0x4>;
867 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
876 reg = <0x0 0x1571000 0x0 0x8>;
878 interrupts = <0 116 0x4>;
883 reg = <0x0 0x1572000 0x0 0x8>;
885 interrupts = <0 126 0x4>;
890 reg = <0x0 0x1573000 0x0 0x8>;
892 interrupts = <0 160 0x4>;
897 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
898 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
900 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>,
901 <0 118 IRQ_TYPE_LEVEL_HIGH>;
907 bus-range = <0x0 0xff>;
908 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
909 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
912 interrupt-map-mask = <0 0 0 7>;
913 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
914 <0000 0 0 2 &gic 0 111 0x4>,
915 <0000 0 0 3 &gic 0 112 0x4>,
916 <0000 0 0 4 &gic 0 113 0x4>;
917 fsl,pcie-scfg = <&scfg 0>;
924 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
925 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
927 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>,
928 <0 128 IRQ_TYPE_LEVEL_HIGH>;
934 bus-range = <0x0 0xff>;
935 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
936 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
939 interrupt-map-mask = <0 0 0 7>;
940 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
941 <0000 0 0 2 &gic 0 121 0x4>,
942 <0000 0 0 3 &gic 0 122 0x4>,
943 <0000 0 0 4 &gic 0 123 0x4>;
951 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
952 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
954 interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>,
955 <0 162 IRQ_TYPE_LEVEL_HIGH>;
961 bus-range = <0x0 0xff>;
962 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
963 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
966 interrupt-map-mask = <0 0 0 7>;
967 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
968 <0000 0 0 2 &gic 0 155 0x4>,
969 <0000 0 0 3 &gic 0 156 0x4>,
970 <0000 0 0 4 &gic 0 157 0x4>;
978 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
979 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
980 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
990 block-offset = <0x10000>;
999 reg = <0x0 0x1ee2140 0x0 0x4>;
1005 reg = <0x0 0x29d0000 0x0 0x10000>;
1006 fsl,rcpm-wakeup = <&rcpm 0x20000>;