Lines Matching +full:ethernet +full:- +full:phy

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 		stdout-path = "serial0:115200n8";
36 		shunt-resistor = <1000>;
67 	#address-cells = <2>;
68 	#size-cells = <1>;
75 			compatible = "cfi-flash";
76 			#address-cells = <1>;
77 			#size-cells = <1>;
79 			big-endian;
80 			bank-width = <2>;
81 			device-width = <1>;
85 			compatible = "fsl,ifc-nand";
86 			#address-cells = <1>;
87 			#size-cells = <1>;
91 		cpld: board-control@2,0 {
92 			compatible = "fsl,ls1043ardb-cpld";
98 	bus-num = <0>;
102 		#address-cells = <1>;
103 		#size-cells = <1>;
104 		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
106 		spi-max-frequency = <1000000>; /* input clock */
107 		fsl,spi-cs-sck-delay = <100>;
108 		fsl,spi-sck-cs-delay = <100>;
114 		spi-max-frequency = <2000000>;
115 		fsl,spi-cs-sck-delay = <100>;
116 		fsl,spi-sck-cs-delay = <50>;
122 		spi-max-frequency = <2000000>;
123 		fsl,spi-cs-sck-delay = <100>;
124 		fsl,spi-sck-cs-delay = <50>;
136 #include "fsl-ls1043-post.dtsi"
139 	ethernet@e0000 {
140 		phy-handle = <&qsgmii_phy1>;
141 		phy-connection-type = "qsgmii";
144 	ethernet@e2000 {
145 		phy-handle = <&qsgmii_phy2>;
146 		phy-connection-type = "qsgmii";
149 	ethernet@e4000 {
150 		phy-handle = <&rgmii_phy1>;
151 		phy-connection-type = "rgmii-id";
154 	ethernet@e6000 {
155 		phy-handle = <&rgmii_phy2>;
156 		phy-connection-type = "rgmii-id";
159 	ethernet@e8000 {
160 		phy-handle = <&qsgmii_phy3>;
161 		phy-connection-type = "qsgmii";
164 	ethernet@ea000 {
165 		phy-handle = <&qsgmii_phy4>;
166 		phy-connection-type = "qsgmii";
169 	ethernet@f0000 { /* 10GEC1 */
170 		phy-handle = <&aqr105_phy>;
171 		phy-connection-type = "xgmii";
175 		rgmii_phy1: ethernet-phy@1 {
179 		rgmii_phy2: ethernet-phy@2 {
183 		qsgmii_phy1: ethernet-phy@4 {
187 		qsgmii_phy2: ethernet-phy@5 {
191 		qsgmii_phy3: ethernet-phy@6 {
195 		qsgmii_phy4: ethernet-phy@7 {
201 		aqr105_phy: ethernet-phy@1 {
202 			compatible = "ethernet-phy-ieee802.3-c45";
211 		compatible = "fsl,ucc-hdlc";
212 		rx-clock-name = "clk8";
213 		tx-clock-name = "clk9";
214 		fsl,rx-sync-clock = "rsync_pin";
215 		fsl,tx-sync-clock = "tsync_pin";
216 		fsl,tx-timeslot-mask = <0xfffffffe>;
217 		fsl,rx-timeslot-mask = <0xfffffffe>;
218 		fsl,tdm-framer-type = "e1";
219 		fsl,tdm-id = <0>;
220 		fsl,siram-entry-id = <0>;
221 		fsl,tdm-interface;