Lines Matching +full:0 +full:x10000
23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39 reg = <0x1>;
41 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 arm,psci-suspend-param = <0x0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
85 #clock-cells = <0>;
101 offset = <0>;
102 mask = <0x02>;
127 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
128 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
136 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
144 thermal-sensors = <&tmu 0>;
199 reg = <0x0 0x1080000 0x0 0x1000>;
208 reg = <0x0 0x1e00000 0x0 0x10000>;
209 ranges = <0x0 0x0 0x1e00000 0x10000>;
214 reg = <0x900 0x4>;
215 #clock-cells = <0>;
216 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
223 reg = <0x0 0x1e60000 0x0 0x10000>;
229 reg = <0x0 0x1e80000 0x0 0x10000>;
237 reg = <0x1c 0x8>;
243 reg = <0x0 0x1fc0000 0x0 0x10000>;
249 reg = <0x0 0x1300000 0x0 0xa0000>;
257 #size-cells = <0>;
258 reg = <0x0 0x2000000 0x0 0x10000>;
268 #size-cells = <0>;
269 reg = <0x0 0x2010000 0x0 0x10000>;
279 #size-cells = <0>;
280 reg = <0x0 0x2020000 0x0 0x10000>;
290 #size-cells = <0>;
291 reg = <0x0 0x2030000 0x0 0x10000>;
301 #size-cells = <0>;
302 reg = <0x0 0x2040000 0x0 0x10000>;
312 #size-cells = <0>;
313 reg = <0x0 0x2050000 0x0 0x10000>;
323 #size-cells = <0>;
324 reg = <0x0 0x2060000 0x0 0x10000>;
334 #size-cells = <0>;
335 reg = <0x0 0x2070000 0x0 0x10000>;
345 #size-cells = <0>;
346 reg = <0x0 0x20c0000 0x0 0x10000>,
347 <0x0 0x20000000 0x0 0x10000000>;
356 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
358 #size-cells = <0>;
359 reg = <0x0 0x2100000 0x0 0x10000>;
364 dmas = <&edma0 0 62>, <&edma0 0 60>;
372 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
374 #size-cells = <0>;
375 reg = <0x0 0x2110000 0x0 0x10000>;
380 dmas = <&edma0 0 58>, <&edma0 0 56>;
388 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
390 #size-cells = <0>;
391 reg = <0x0 0x2120000 0x0 0x10000>;
396 dmas = <&edma0 0 54>, <&edma0 0 2>;
405 reg = <0x0 0x2140000 0x0 0x10000>;
407 clock-frequency = <0>; /* fixed up by bootloader */
418 reg = <0x0 0x2150000 0x0 0x10000>;
420 clock-frequency = <0>; /* fixed up by bootloader */
432 reg = <0x0 0x2180000 0x0 0x10000>;
444 reg = <0x0 0x2190000 0x0 0x10000>;
456 reg = <0x00 0x21c0500 0x0 0x100>;
465 reg = <0x00 0x21c0600 0x0 0x100>;
475 reg = <0x0 0x2260000 0x0 0x1000>;
488 reg = <0x0 0x2270000 0x0 0x1000>;
501 reg = <0x0 0x2280000 0x0 0x1000>;
514 reg = <0x0 0x2290000 0x0 0x1000>;
527 reg = <0x0 0x22a0000 0x0 0x1000>;
540 reg = <0x0 0x22b0000 0x0 0x1000>;
554 reg = <0x0 0x22c0000 0x0 0x10000>,
555 <0x0 0x22d0000 0x0 0x10000>,
556 <0x0 0x22e0000 0x0 0x10000>;
570 reg = <0x0 0x2300000 0x0 0x10000>;
581 reg = <0x0 0x2310000 0x0 0x10000>;
592 reg = <0x0 0x2320000 0x0 0x10000>;
603 reg = <0x0 0x3100000 0x0 0x10000>;
606 snps,quirk-frame-length-adjustment = <0x20>;
613 reg = <0x0 0x3110000 0x0 0x10000>;
616 snps,quirk-frame-length-adjustment = <0x20>;
623 reg = <0x0 0x3200000 0x0 0x10000>,
624 <0x7 0x100520 0x0 0x4>;
634 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
635 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
645 bus-range = <0x0 0xff>;
646 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
647 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
650 interrupt-map-mask = <0 0 0 7>;
651 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
652 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
653 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
654 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
655 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
661 reg = <0x00 0x03400000 0x0 0x00100000
662 0x80 0x00000000 0x8 0x00000000>;
673 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
674 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
684 bus-range = <0x0 0xff>;
685 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
686 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
689 interrupt-map-mask = <0 0 0 7>;
690 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
691 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
692 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
693 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
694 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
700 reg = <0x00 0x03500000 0x0 0x00100000
701 0x88 0x00000000 0x8 0x00000000>;
712 reg = <0 0x5000000 0 0x800000>;
715 stream-match-mask = <0x7c00>;
724 /* performance counter interrupts 0-7 */
763 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
767 ranges = <0x0 0x00 0x8000000 0x100000>;
768 reg = <0x00 0x8000000 0x0 0x100000>;
773 compatible = "fsl,sec-v5.0-job-ring",
774 "fsl,sec-v4.0-job-ring";
775 reg = <0x10000 0x10000>;
780 compatible = "fsl,sec-v5.0-job-ring",
781 "fsl,sec-v4.0-job-ring";
782 reg = <0x20000 0x10000>;
787 compatible = "fsl,sec-v5.0-job-ring",
788 "fsl,sec-v4.0-job-ring";
789 reg = <0x30000 0x10000>;
794 compatible = "fsl,sec-v5.0-job-ring",
795 "fsl,sec-v4.0-job-ring";
796 reg = <0x40000 0x10000>;
803 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
804 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
805 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
815 block-offset = <0x10000>;
823 reg = <0x0 0xc000000 0x0 0x1000>;
833 reg = <0x0 0xc010000 0x0 0x1000>;
843 reg = <0x0 0xf080000 0x0 0x10000>;
844 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
845 <0 223 IRQ_TYPE_LEVEL_HIGH>;
853 arm,malidp-arqos-value = <0xd000d000>;
864 reg = <0x0 0xf0c0000 0x0 0x10000>;
874 #sound-dai-cells = <0>;
876 reg = <0x0 0xf100000 0x0 0x10000>;
895 #sound-dai-cells = <0>;
897 reg = <0x0 0xf110000 0x0 0x10000>;
916 #sound-dai-cells = <0>;
918 reg = <0x0 0xf120000 0x0 0x10000>;
937 #sound-dai-cells = <0>;
939 reg = <0x0 0xf130000 0x0 0x10000>;
958 #sound-dai-cells = <0>;
960 reg = <0x0 0xf140000 0x0 0x10000>;
979 #sound-dai-cells = <0>;
981 reg = <0x0 0xf150000 0x0 0x10000>;
1001 reg = <0x0 0xf1f0000 0x0 0x10000>;
1002 #clock-cells = <0>;
1008 reg = <0x0 0x1f80000 0x0 0x10000>;
1009 interrupts = <0 23 0x4>;
1010 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
1011 fsl,tmu-calibration = <0x00000000 0x00000024
1012 0x00000001 0x0000002b
1013 0x00000002 0x00000031
1014 0x00000003 0x00000038
1015 0x00000004 0x0000003f
1016 0x00000005 0x00000045
1017 0x00000006 0x0000004c
1018 0x00000007 0x00000053
1019 0x00000008 0x00000059
1020 0x00000009 0x00000060
1021 0x0000000a 0x00000066
1022 0x0000000b 0x0000006d
1024 0x00010000 0x0000001c
1025 0x00010001 0x00000024
1026 0x00010002 0x0000002c
1027 0x00010003 0x00000035
1028 0x00010004 0x0000003d
1029 0x00010005 0x00000045
1030 0x00010006 0x0000004d
1031 0x00010007 0x00000055
1032 0x00010008 0x0000005e
1033 0x00010009 0x00000066
1034 0x0001000a 0x0000006e
1036 0x00020000 0x00000018
1037 0x00020001 0x00000022
1038 0x00020002 0x0000002d
1039 0x00020003 0x00000038
1040 0x00020004 0x00000043
1041 0x00020005 0x0000004d
1042 0x00020006 0x00000058
1043 0x00020007 0x00000063
1044 0x00020008 0x0000006e
1046 0x00030000 0x00000010
1047 0x00030001 0x0000001c
1048 0x00030002 0x00000029
1049 0x00030003 0x00000036
1050 0x00030004 0x00000042
1051 0x00030005 0x0000004f
1052 0x00030006 0x0000005b
1053 0x00030007 0x00000068>;
1060 reg = <0x01 0xf0000000 0x0 0x100000>;
1065 bus-range = <0x0 0x0>;
1067 msi-map = <0 &its 0x17 0xe>;
1068 iommu-map = <0 &smmu 0x17 0xe>;
1070 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
1072 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
1074 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
1076 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
1078 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
1080 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
1082 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
1084 enetc_port0: ethernet@0,0 {
1086 reg = <0x000000 0 0 0 0>;
1090 enetc_port1: ethernet@0,1 {
1092 reg = <0x000100 0 0 0 0>;
1096 enetc_port2: ethernet@0,2 {
1098 reg = <0x000200 0 0 0 0>;
1109 enetc_mdio_pf3: mdio@0,3 {
1111 reg = <0x000300 0 0 0 0>;
1113 #size-cells = <0>;
1116 ethernet@0,4 {
1118 reg = <0x000400 0 0 0 0>;
1124 mscc_felix: ethernet-switch@0,5 {
1125 reg = <0x000500 0 0 0 0>;
1132 #size-cells = <0>;
1135 mscc_felix_port0: port@0 {
1136 reg = <0>;
1184 enetc_port3: ethernet@0,6 {
1186 reg = <0x000600 0 0 0 0>;
1197 rcec@1f,0 {
1198 reg = <0x00f800 0 0 0 0>;
1207 reg = <0x01 0xf0800000 0x0 0x10000>;
1213 reg = <0x0 0x2800000 0x0 0x10000>;
1224 reg = <0x0 0x2810000 0x0 0x10000>;
1235 reg = <0x0 0x2820000 0x0 0x10000>;
1246 reg = <0x0 0x2830000 0x0 0x10000>;
1257 reg = <0x0 0x2840000 0x0 0x10000>;
1268 reg = <0x0 0x2850000 0x0 0x10000>;
1279 reg = <0x0 0x2860000 0x0 0x10000>;
1290 reg = <0x0 0x2870000 0x0 0x10000>;
1300 reg = <0x0 0x1e34040 0x0 0x1c>;
1307 reg = <0x0 0x2800000 0x0 0x10000>;
1308 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1315 reg = <0x0 0x2810000 0x0 0x10000>;
1316 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;